ASML Holding NV (ASML) Report Interpretation

Overview

This primer explains why Bernstein views High-NA EUV as the next step in semiconductor scaling and a long-term positive for ASML. The report argues that its superior resolution and contrast can lower total patterning cost even though the new scanners face a structural throughput penalty from half-field exposure.

Core views

Bernstein’s central thesis is that shrinking in both logic and DRAM will continue, driven by demand for greater compute and memory density from AI, cloud computing, high-performance computing and advanced mobile devices. Logic metal pitch is expected to decline from roughly 40nm at N7 in 2018 to about 21nm at A14 around 2027 and potentially 14–10nm beyond A2. DRAM feature size is expected to move from roughly 17–18nm at 1Y to around 10nm at 1d and ultimately toward 7–8nm. At these dimensions, Low-NA EUV increasingly requires double or triple patterning, adding masks, lithography-etch loops, cost, cycle time and defect opportunities. Bernstein therefore sees higher-resolution lithography as a prerequisite for continued node migration rather than a discretionary upgrade. High-NA EUV raises numerical aperture from 0.33 to 0.55 while retaining the 13.5nm EUV wavelength. Bernstein says this improves demonstrated resolution from roughly 13nm to roughly 8nm, allowing approximately 1.7x smaller features and up to 2.8x higher pattern density. Higher contrast improves local critical-dimension uniformity by around 40%, reduces pattern variability by 1.4x and lowers dose by 1.4x. These advantages can replace multi-patterned Low-NA flows with single High-NA exposures, reducing masks, non-lithography processing, cycle time and defect risk. The report cites roughly 20% to 35% cost benefits for critical layers and estimates lithography capex and opex can be about 1.2x higher in a High-NA single-exposure flow even as total patterning cost falls, shifting value from etch, deposition and other non-lithography steps to ASML’s equipment. The technological trade-off is the EXE platform’s anamorphic optics. Its 4x-by-8x demagnification retains standard reticles but reduces the wafer exposure field from roughly 26 × 33mm to 26 × 16.5mm. The smaller field requires about twice as many exposures to cover a wafer and can require AB stitching for large logic dies, reducing productivity and adding overlay, continuity and routing complexity. High-NA also has a depth-of-focus margin roughly 2.5–3x smaller than Low-NA. ASML partly offsets these constraints through an 8g wafer stage, versus roughly twice the Low-NA acceleration, a 32g reticle stage, versus roughly four times, lower dose and higher source power. Still, Bernstein stresses that High-NA remains structurally below Low-NA on scanner throughput: the later Low-NA roadmap reaches 300–330 WPH, versus just over 210 WPH on the current High-NA roadmap. Tool maturity is central to the economics. The EXE:5200B achieved 175 WPH in AA mode, matched-machine overlay of no more than 0.8nm and customer availability above 80%; ASML targets 90% availability by Q4 2026 and roughly 95% over the following three to four years. Bernstein estimates that moving to 95% availability would cut the cost of a one-mask High-NA exposure by 23%, from about €82 to about €63. For large stitched dies, current EXE:5200B AB throughput is 135 WPH versus 175 WPH in AA, a roughly 23% reduction. The report estimates 2025 lithography-equipment cost per High-NA exposure at 2.4x Low-NA for AA and 3.1x for AB, narrowing by 2030 to 1.9x and 2.1x, respectively. It therefore judges economics on the full patterning flow rather than scanner WPH or a single exposure in isolation. DRAM is expected to be the earlier and broader adopter because its smaller die generally avoid stitching. At 15nm contact holes, Bernstein says a flow requiring two Low-NA EUV exposures plus one DUV exposure can be replaced by one High-NA exposure, delivering a reported 30% cost benefit and fewer masks, steps, defects and floor-space needs. Across P40–P28 DRAM contact-hole pitches, High-NA achieved LCDU of 1.4–2.3nm at doses of 45–53 mJ/cm², compared with Low-NA LCDU of 2.4–3.6nm at practical doses of roughly 63–73 mJ/cm². Bernstein notes that Low-NA would theoretically require 191–238 mJ/cm² to match High-NA LCDU, underpinning an estimated 50% High-NA single-exposure cost benefit versus Low-NA when LCDU is equalized. The report expects Samsung and SK hynix to lead broader DRAM insertion around D1d in 2027, while Micron could follow later. Logic adoption is more gradual because large CPUs and GPUs may require stitching, but Bernstein sees attractive early use cases at the tightest layers. For P36 logic vias, the report cites High-NA printing defect-free contact holes at 77 mJ/cm² and 136 WPH, versus Low-NA at 250 mJ/cm² and 52 WPH with deformed holes. At P30, High-NA can replace a double-exposure Low-NA flow with an estimated 20% cost benefit; at P19 local interconnect, it can replace three Low-NA exposures with one and reduce lithography cost by around 35%. Intel has validated High-NA in high-volume production on selected 18A layers, and Bernstein expects wider Intel use at A14. It expects Samsung and TSMC to adopt meaningfully around A10-class nodes near 2030 as availability and throughput improve. For ASML, Bernstein expects HNA to reinforce a structural rise in lithography intensity. Lithography represented about 23–25% of WFE since 2023, compared with historical high-teens to low-twenties levels; ASML’s WFE share increased from roughly 16% in 2022 to around 22% in 2025. The report projects overall lithography intensity to rise from 24% to 26%. In DRAM, intensity rose from around 20% at 1Y and 1Z to 26% at 1c and could reach about 30% at 1d with double-patterning EUV or HNA. Logic intensity remains around 32% after exceeding 35% at 5nm and 3nm, and Bernstein expects it to remain similar or rise with HNA at 1.4nm and 1nm. Slower HNA adoption does not weaken the long-term case in Bernstein’s view and may support ASML near term by extending demand for higher-margin Low-NA EUV tools before customers consolidate layers on High-NA systems. Beyond High-NA, Bernstein describes Hyper-NA as a potential next option, not a committed product. It could raise NA toward 0.75 while reusing common platform components and become relevant around A3 as logic metal pitch approaches 12–16nm, after High-NA’s expected extension toward roughly 18nm pitch.

Analysis framework

Bernstein begins with logic and DRAM scaling roadmaps, then explains lithography’s role in feature-size reduction. It compares High-NA’s resolution, contrast, throughput and field-size trade-offs with Low-NA EUV, models cost at the full patterning-flow level, and applies the results separately to logic and DRAM use cases. The report then links adoption timing and lithography intensity to ASML’s equipment demand and valuation.

Methodology notes

• Industry AnalysisSupply-demand framework

  Logic and DRAM technology roadmaps linked to rising compute and memory-density demand

  The report uses expected feature-size and pitch reduction in logic and DRAM to explain why more advanced lithography capacity is needed.

• Industry AnalysisVolume-price decomposition

  Full-patterning-flow cost comparison of High-NA versus Low-NA multi-patterning

  Rather than comparing scanner throughput alone, Bernstein combines exposures, masks, stitching, availability, dose and non-lithography process steps to assess total patterning economics.

• Valuation methodsP/E and PEG Valuation

  Price-to-earnings valuation

  Bernstein applies a 40x P/E multiple to its Q5-8 EPS estimate to derive the rounded €2,500 price target.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• ASML Holding NV (ASML)

  Primary covered company and expected beneficiary of higher EUV adoption and lithography intensity.

  Strengths

  Over 90% overall lithography market share and a monopoly position in EUV; High-NA can shift more critical-layer spending into lithography.

  Weaknesses

  High-NA economics initially face lower availability and structurally lower throughput than Low-NA due to half-field exposure.

  Comparison

  High-NA can be cheaper than complex Low-NA multi-patterning, especially in DRAM, but may remain more expensive than Low-NA double patterning for some large stitched logic dies over the next five years.

  Risks

  Margins below expectations, China over-stocking, weaker WFE demand, slower technology migration, alternative technologies and tighter China export controls.

Key data

• ASML rating and price targetOutperform; €2,500Bernstein reiterates Outperform and calls ASML a top pick.
• Current price and implied upside€1,435.40; 107.6%Ticker-table figures for ASML.NA as of 1 September 2026.
• High-NA resolution~8nm versus ~13nm for Low-NA EUV0.55 NA versus 0.33 NA, while retaining a 13.5nm wavelength.
• High-NA availability economics~€82 to ~€63 per exposureBernstein estimates a 23% cost decline when availability reaches 95%.
• HNA deployment timingDRAM around 2027; broader logic 2028–2030Intel is already using High-NA on selected 18A layers in high-volume production.
• Lithography intensity24% to 26%Bernstein expects blended intensity to rise, with DRAM potentially reaching ~30% at 1d.

Impact & implications

The report argues that High-NA adoption should raise ASML’s exposure to structurally growing lithography spending by replacing multi-step patterning flows with more lithography-intensive single-exposure solutions. Near-term delays in broad adoption may preserve demand for higher-margin Low-NA tools, while the longer-term benefit comes from increased EUV layers and higher lithography intensity in DRAM and advanced logic.

Risks

• ASML margins could fall below expectations because of the cost of commercializing EUV and advancing it to new generations.
• Larger-than-expected China over-stocking, a weaker WFE market or slower technology migration could pressure demand.
• Further tightened export controls on China customers could affect ASML.
• Alternative technologies could pose a longer-term threat.
• High-NA availability, throughput, stitching and resist-process maturity remain execution constraints.

What to watch

• Progress toward ASML’s 90% High-NA availability target by Q4 2026 and roughly 95% over the following three to four years.
• Follow-on High-NA orders and qualification activity from DRAM customers in 2H 2026 and 2027.
• The pace of Samsung and SK hynix DRAM adoption around D1d and Intel’s broader use at A14.
• Whether TSMC and Samsung move toward High-NA insertion at A10-class nodes around 2030.
• High-NA productivity improvements from source power, optical transmission and future EXE platforms.