Bernstein raises ASML target price to €2,300, based on High-NA EUV ramp and rising lithography intensity

Overview

This report focuses on ASML’s High-NA EUV costs, adoption pace, and financial impact. Bernstein argues that market concerns that High-NA EUV costs are too high and adoption will be delayed overlook differences among DRAM and logic chips in chip size, number of masks, and stitching requirements. Because DRAM can usually be exposed with a single mask, the economics of High-NA EUV become valid earlier for DRAM; logic chips, especially large GPU/CPU dies, have slower adoption because of split-field exposures and stitching costs.

Core views

The core thesis is: first, DRAM will adopt High-NA EUV earlier than logic, with Samsung and SK hynix potentially ramping at the 1d node in 2027; second, logic adoption is also visible, with Intel likely to be first at the A14 node in 2028, followed by Samsung logic, while TSMC may be delayed until around 2030; third, as High-NA EUV tool availability and throughput improve, per-exposure cost should fall significantly; fourth, High-NA EUV can replace complex multiple-patterning workflows, raising lithography’s share of overall fab capex; fifth, AI-driven advanced logic and DRAM expansion should support upward revisions to ASML’s long-cycle revenue and earnings.

Analysis framework

The report compares High-NA EUV with Low-NA EUV on resolution, numerical aperture, exposure field size, mask count, throughput, equipment availability, and per-exposure cost, deriving the adoption economics for DRAM and logic customers. It then updates ASML revenue, margin, EPS, and target price assumptions using DRAM and logic process roadmaps, customer adoption timing, EUV/DUV shipment forecasts, and valuation multiples.

Methodology notes

• Technical cost-effectiveness analysisHigh-NA EUV versus Low-NA EUV cost-per-exposure comparison

  Compares High-NA EUV and Low-NA EUV in terms of cost per exposure under single-mask versus double-mask, tool availability, and throughput conditions.

  The report argues High-NA EUV’s current cost premium mainly reflects lower tool availability and the need for AB double-mask stitching on large logic dies; as availability improves from roughly 80%-85% to close to 95% and throughput rises, the cost gap should narrow.

• Industry roadmap analysisDRAM and logic node adoption roadmap

  Uses DRAM 1d node and logic A14/A10 nodes to time High-NA EUV adoption.

  Because DRAM dies are smaller and generally do not require stitching, the economic case for High-NA EUV is valid earlier; large logic dies require half-field stitching, so adoption depends more on tool maturity and lower total process costs.

• Valuation approachTarget P/E multiple valuation

  Raises the target price by increasing the target P/E multiple.

  The report raises ASML’s target P/E from 35x to 40x and lifts the target price to €2,300 by combining higher revenue, margin, and EPS forecasts.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• ASML HOLDING NV

  Core beneficiary

  Strengths

  Both High-NA EUV and Low-NA EUV are at the core of advanced-node lithography; AI-driven advanced logic and DRAM expansion increase equipment demand; the report upgrades 2030 revenue and EPS forecasts.

  Weaknesses

  Early High-NA EUV tool availability is lower and costs are higher, and adoption pace remains dependent on customer process roadmaps.

  Comparison

  The report believes ASML is currently trading at a valuation discount to peers, but there is room to revise profitability forecasts and target multiples higher.

  Risks

  Delay in High-NA EUV adoption, slower AI-related capex by customers, weaker-than-expected demand for advanced nodes, and slower-than-expected improvements in availability and throughput.

• DRAM manufacturers

  Early adopters of High-NA EUV

  Strengths

  DRAM dies are smaller and usually do not need double-mask stitching, so the economics of High-NA EUV are valid earlier.

  Weaknesses

  Adoption pace still depends on 1d-node ramp, capex levels, and equipment deliveries.

  Comparison

  Compared with large logic dies, DRAM faces lower cost barriers for High-NA EUV adoption.

  Risks

  DRAM demand volatility, capex cuts, and delays in node transitions.

• Advanced logic foundries

  Subsequent adopters

  Strengths

  High-NA EUV can reduce complex multiple-patterning flows and improve process efficiency over time.

  Weaknesses

  Large logic dies require AB double-mask stitching, lowering throughput and raising costs.

  Comparison

  Intel may adopt High-NA EUV ahead of Samsung logic and TSMC; TSMC is expected to be more cautious and likely to delay until around 2030.

  Risks

  Yield and design complexity constraints on stitching, tool maturity, and customers opting to extend Low-NA EUV workflows.

Key data

• ASML ratingOutperformBernstein maintains ASML Outperform relative to the market.
• ASML target price€2,300Target price raised from the prior €1,700.
• Current price€1,634.40ASML.NA price as of July 3, 2026 in the table.
• 2027 EUV shipment forecast91 unitsHigher than the prior 86-unit forecast.
• 2028 EUV shipment forecast113 unitsHigher than the prior 87-unit forecast.
• 2030 EUV revenue forecast€42.7bnReport expects EUV revenue to grow at about 30% CAGR.
• 2030 ASML revenue forecast€79.7bnAround 24% above consensus expectations.
• 2030 ASML EPS forecast€96.86Around 50% above consensus expectations.
• Overall lithography intensity forecast24% in 2025 to 26% in 2028Mainly driven by DRAM and advanced logic.
• DRAM lithography intensityabout 30% on 1d nodesDriven by more EUV layers and the introduction of High-NA EUV or double-patterning.
• High-NA EUV resolutionaround 8nmHigher resolution versus Low-NA EUV’s roughly 13nm.
• High-NA EUV availability improvement targetclose to 95%The report says higher availability can lower per-exposure High-NA costs by about 23%.

Impact & implications

For ASML, longer-cycle adoption of High-NA EUV and AI-driven advanced-node expansion are expected to lift EUV and DUV demand and increase lithography’s share of fab equipment spending. Even if TSMC adopts High-NA EUV more slowly in the near term, the report argues this is not necessarily negative, as additional Low-NA EUV shipments may also support ASML revenue and margins in the nearer term. For the storage and logic supply chain, DRAM vendors may be early beneficiaries of High-NA EUV, while adoption speed for large logic chips will depend on stitching costs, tool maturity, and total process savings.

Risks

• High-NA EUV client adoption occurs later than expected, particularly if logic customers delay ramp.
• Availability, throughput, or cost declines of High-NA EUV equipment improve more slowly than assumed.
• AI-related advanced logic and DRAM expansion cycles underperform, leading to EUV/DUV order levels below expectations.
• Stitching yield, yield-related losses, and design complexity in large logic dies restrict the addressable scope of High-NA EUV.
• The assumption of a higher ASML multiple does not materialize, or semiconductor equipment peers re-rate lower.
• Geopolitical risk, export controls, or customer capex swings affect ASML shipments.

What to watch

• The actual ramp cadence of High-NA EUV at DRAM 1d nodes by SK hynix, Samsung, and Micron.
• High-NA EUV adoption signals at Intel A14, Samsung SF1.4, and TSMC A10 logic nodes.
• Whether ASML EXE-series tool availability rises to 90% as guided and further approaches 95%.
• Throughput improvements and AB stitching efficiency of EXE:5200C, EXE:5200D, and EXE:5400E.
• Whether ASML EUV shipments, DUV demand, gross margin, and operating margin align with the revision case.
• Whether DRAM and advanced logic capex remains supported by AI demand.