ASML raised its target price to €2,300, with the core drivers being High-NA EUV adoption and rising lithography intensity

Overview

This report focuses on the economics, adoption pace, and financial impact of ASML's High-NA EUV. Bernstein believes the market's concern that High-NA EUV is too expensive and hard to adopt in the near term overlooks differences in chip size, mask count, and stitching requirements between DRAM and logic chips. Because DRAM typically does not need double-mask stitching used for large logic chips, the cost of High-NA EUV exposure in DRAM is easier to justify, so it is expected to be introduced before logic chips.

Core views

The core views are: first, High-NA EUV improves resolution from about 13nm to about 8nm by increasing NA from 0.33 to 0.55, reducing multi-patterning steps; second, current High-NA EUV cost is high mainly because utilization and throughput are constrained, but the utilization and WpH roadmap is improving; third, DRAM is expected to introduce High-NA EUV around 1d around 2027, with Intel likely to be first among logic nodes in 2028 and TSMC potentially delaying to around 2030; fourth, AI-driven advanced logic and DRAM capex buildout support higher ASML EUV and DUV demand than previously assumed.

Analysis framework

The report compares High-NA EUV versus Low-NA EUV across resolution, mask count, field exposure, AA/AB throughput, tool utilization, exposure cost, and total process cost, derives the expected adoption sequence for different chip types, and further maps this to lithography intensity, EUV shipments, revenue, margins, EPS, and target valuation multiples.

Methodology notes

• Technical cost comparisonHigh-NA EUV vs Low-NA EUV exposure cost framework

  Compares per-exposure cost by tool utilization, throughput, mask count, and stitching requirements.

  The report distinguishes DRAM small-chip AA single-mask scenarios from large logic AB double-mask stitching scenarios, noting that AB throughput is lower, making early High-NA EUV more expensive for logic chips.

• Semiconductor process-route analysisLithography intensity transition framework

  When High-NA EUV replaces Low-NA EUV multi-patterning, value shifts from etch, deposition, and cleaning steps toward lithography.

  Although individual High-NA EUV exposure cost is higher, it can reduce mask count, litho-etch loops, and non-lithography steps, so total process cost may fall and ASML's share of fab capex may rise.

• Valuation methodologyTarget P/E valuation

  Raises target P/E based on higher long-term revenue, margins, and EPS, and derives target price accordingly.

  The report increases target P/E from 35x to 40x, citing an accelerated capex cycle, higher peer valuations, and upward revisions to ASML's long-term earnings outlook.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• ASML HOLDING NV

  Core beneficiary

  Strengths

  As a critical supplier of EUV and High-NA EUV lithography equipment, ASML benefits from AI-driven advanced logic and DRAM expansion, as well as rising lithography intensity.

  Weaknesses

  Early High-NA EUV tool cost is high, utilization is low, and stitching is required for larger logic chips, so adoption cadence remains uncertain in the near term.

  Comparison

  The report believes ASML is currently valued at a relative discount versus peers, while the magnitude of long-term revenue and EPS upside is greater than market expectations.

  Risks

  If High-NA EUV utilization, throughput, or customer adoption pace falls short of expectations, the valuation and earnings upside case could weaken.

• DRAM vendors

  Potential early adopters of High-NA EUV

  Strengths

  DRAM chip sizes are smaller and usually do not require double-mask stitching like large logic chips, making High-NA EUV cost easier to justify.

  Weaknesses

  EUV adoption strategies and capex pacing differ by vendor, with Micron possibly more conservative than SK hynix and Samsung.

  Comparison

  The report sees SK hynix and Samsung potentially leading with High-NA EUV adoption around the 1d node near 2027.

  Risks

  Memory-cycle volatility, capex cuts, or delayed process nodes could affect equipment demand.

• Advanced logic vendors

  Later-stage adopters of High-NA EUV

  Strengths

  On advanced nodes such as A14, SF1.4, and A10, High-NA EUV can reduce multi-patterning complexity.

  Weaknesses

  Larger GPU/CPU die often require AB double-mask stitching, making early adoption costs higher than DRAM scenarios.

  Comparison

  The report expects Intel may lead in 2028, followed by Samsung logic, with TSMC likely moving to broader adoption around 2030.

  Risks

  If Low-NA EUV multi-patterning continues to be extended, High-NA EUV adoption could be further delayed.

Key data

• ASML ratingOutperformThe report maintains a positive rating on ASML.
• ASML target price€2,300Target price raised from previous target price of €1,700.
• ASML current price€1,634.40The table date is shown as July 3, 2026.
• 2028 EUV shipment forecast113 unitsPrevious forecast was 87 units, reflecting advanced logic and DRAM buildout.
• 2030 EUV revenue forecast€42.7bnThe report says this is more than 30% above market expectations.
• 2030 ASML revenue forecastabout €80bnCompared with consensus of about €64.4bn, Bernstein's estimate is roughly 24% higher.
• 2030 EPS forecast€96.86The report says this is about 50% above consensus.
• Overall lithography intensity forecast24% in 2025 to 26% in 2028Mainly driven by DRAM and advanced logic.
• DRAM lithography intensityabout 30% at 1d nodeSupported by higher EUV layer counts and the introduction of High-NA EUV or double-patterning.
• High-NA EUV utilization targetabout 95%The report expects this to gradually approach mature Low-NA EUV levels over the next 3 to 5 years.

Impact & implications

If the report's thesis holds, ASML would benefit not only from High-NA EUV uptake but also from continued sales of more Low-NA EUV tools while High-NA EUV adoption ramps, which may even be better for short-term margins. Over the long term, as DRAM and advanced logic increase process complexity, lithography's share of semiconductor capex rises, creating upside for ASML's revenue, gross margin, operating margin, and EPS.

Risks

• Slower-than-expected improvements in High-NA EUV tool utilization and throughput versus roadmap, causing exposure-cost declines to underperform.
• Actual adoption timelines from customers such as TSMC, Intel, Samsung, SK hynix, and Micron come in later than the report's assumptions.
• AI-driven advanced logic and DRAM capex cycles are lower than expected, leading to overly high EUV and DUV shipment forecasts.
• High-NA EUV stitching, yield, mask, and ecosystem cost issues may weaken the economic case for logic adoption.
• ASML's manufacturing, supply chain, or service capacity may be insufficient to convert demand into revenue.
• If market valuation multiples compress, the 40x target P/E assumption may be difficult to sustain.

What to watch

• Whether ASML EXE-series High-NA EUV tool utilization rises to 90% or higher in line with the roadmap.
• AA/AB throughput progress for EXE:5200B, EXE:5200C, EXE:5200D, and EXE:5400E.
• Mass-production signals from SK hynix and Samsung on High-NA EUV at the DRAM 1d node.
• High-NA EUV rollout timing at Intel A14, Samsung SF1.4, and TSMC A10 nodes.
• Whether DRAM and advanced logic capex continues to be revised upward by AI demand.
• Whether ASML's EUV, DUV shipments, ASP, gross margin, and operating leverage are approaching the report's forecast.