AI semiconductor supply chain Report Interpretation

Overview

Morgan Stanley examines whether AI semiconductor growth can remain strong into 2028 as cloud-service-provider capex growth moderates. Its conclusion is that compute-chip and advanced-packaging demand should still outgrow overall AI infrastructure spending, supported by large chip sizes, broader use of 2.5D packaging, and expanding GPU and ASIC deployments.

Core views

Morgan Stanley’s central view is that AI semiconductor capex, particularly compute chips, should outgrow overall AI capex in 2028. While Morgan Stanley’s US internet research projects CSP capex growth of 12% into 2028, this report forecasts 50% aggregate growth in 2.5D packaging capacity. The institution argues that AI semiconductor demand can remain stronger because larger chip sizes and an expanding mix of AI GPUs, XPUs, CPUs and networking chips require more advanced packaging. It expects infrastructure spending such as shell and AI data-center construction to be broadly flat in 2028 and memory pricing to be moderate, contrasting with continued chip and packaging growth. The capacity outlook centers on CoWoS, CoPoS and Intel’s EMIB-T, all converted into 12-inch CoWoS-wafer equivalents for comparison. Morgan Stanley expects TSMC CoWoS capacity to rise from 130kwpm in 2026 and 200kwpm in 2027 to 260kwpm in 2028, with expansion principally in Arizona AP9/10 and potentially AP7. TSMC is conducting CoPoS trial production in Taoyuan; if progress is successful, the report expects initial CoPoS capacity build-out at AP9/10 or AP7P3. CoPoS is estimated at 5-10kwpm in 2028 and 10-20kwpm in 2029, although that outlook depends on trial-production results. Outside TSMC, Morgan Stanley expects the non-TSMC CoWoS camp to reach 110kwpm by the end of 2028, from 80kwpm at the end of 2027. ASE/SPIL’s combined FoCoS and CoWoS capacity is projected to rise from 30kwpm to 50-60kwpm, while Amkor’s CoWoS capacity is expected to expand from 30kwpm to 55-60kwpm, with both focusing on CoWoS-L and CoWoS-R. The report also expects TSMC to require additional OS partners beyond ASE, with Amkor and Xintec diversifying oS production in the US and Taiwan. For Intel, the report forecasts average EMIB-T capacity increasing from about 5kwpm in 2026 to 15-20kwpm in 2027 and 40-45kwpm in 2028. EMIB-M capacity is estimated at 110kwpm currently but is expected to fall to 95kwpm in 2027 as capacity converts toward EMIB-T. The report estimates that 40-45kwpm of EMIB-T could produce at least 2mn Humufish substrates and account for 10-15% of 2.5D packaging capacity. It further expects MediaTek/Google Humufish to consume most relevant capacity in 2027-28, with Intel EMIB-T potentially producing close to 3mn Humufish units from late 2027 through 2028 if the supply chain executes well. ASIC developments reinforce the demand outlook. Broadcom’s FY27 revenue guidance was raised to US$115bn and could double again in FY28, while Morgan Stanley’s supply-chain checks indicate that a Broadcom-supported US AI lab customer may book roughly 15k-30k CoWoS wafers in 2027. The report also sees a growing probability that MediaTek could win a second AI CSP or AI-lab customer through its Nvidia NVLink Fusion partnership; a decision in 4Q26 could be a significant catalyst. Qualcomm’s ASIC partnership with AWS is viewed as having limited impact on Alchip because the announced product appears inference-focused, unlike Alchip’s Trainium4 exposure to both training and inference. The report identifies a more constrained near-term area in the OSAT supply chain. Industry checks suggest ASE and Amkor CoWoS expansion is slower than Morgan Stanley’s earlier expectations and customers’ forecasts. Consequently, it now expects a slower ramp for AMD Venice CPU, a major customer of ASE and Amkor capacity. AMD’s total CoWoS consumption is forecast to rise 165% year on year to 345k wafers in 2027, with TSMC bookings rising 200% to 210k wafers. However, the slower OSAT ramp could require TSMC to supply around 80k CoWoS-L wafers for Venice, partly displacing capacity otherwise used for AI GPUs. Venice bookings are expected to rise from 50k wafers in 2026 to 210k in 2027, implying 4.4mn CPU units, below Morgan Stanley’s prior 5.6mn forecast. Across the broader demand picture, global CoWoS demand is estimated to increase from 1,394k wafers in 2026 to 2,509k in 2027. The report projects AI HBM consumption of up to 44bn Gb in 2027, versus up to 29bn Gb in 2026, and AI wafer consumption of at least US$55bn in 2027, versus at least US$27bn in 2026. It also expects AI chip revenue for NVIDIA and AMD data-center/HPC operations to continue rising sequentially and estimates TSMC’s AI-related revenue could achieve a 60% CAGR over 2024-29. Recent August rack recovery and a revised 2026 forecast of 80-85k GB200/GB300 NVL72 racks are cited as evidence of stronger Blackwell GPU consumption.

Analysis framework

Morgan Stanley combines Asian supply-chain checks with company data and internal estimates. It compares projected CSP capex with capacity additions across advanced-packaging technologies, converts differing packaging technologies into 12-inch CoWoS-wafer equivalents, and translates wafer allocations into chip shipments, HBM demand and wafer-revenue estimates.

Methodology notes

• Industry AnalysisSupply-demand framework

  Advanced-packaging capacity and AI chip demand analysis

  The report compares expected CoWoS, CoPoS and EMIB-T capacity with projected GPU, CPU and ASIC demand to assess whether packaging supply can support AI semiconductor growth.

• Industry AnalysisUpstream-Midstream-Downstream Transmission

  AI demand transmission through cloud capex, chips, packaging, HBM and server racks

  Morgan Stanley links CSP capital spending and AI rack deployments to demand for compute chips, advanced packaging, memory and foundry wafers.

• Industry AnalysisVolume-price decomposition

  Wafer-volume, chip-shipment and wafer-revenue estimates

  The report uses capacity allocations, chips per wafer, die geometry and assumed wafer prices to estimate AI wafer consumption and revenue.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• TSMC

  Primary advanced-packaging supplier positioned for continued AI compute demand

  Strengths

  CoWoS capacity is projected to reach 260kwpm in 2028; CoPoS trial production could open another growth path.

  Comparison

  Expected 2028 CoWoS capacity materially exceeds the combined 110kwpm expected from ASE/SPIL and Amkor.

  Risks

  CoPoS expansion depends on successful trial production; supporting Venice could partly crowd out AI GPU capacity.

• AMD (AMD)

  AI GPU and Venice CPU demand require substantial CoWoS capacity

  Strengths

  Total 2027 CoWoS consumption is estimated to rise 165% year on year to 345k wafers.

  Weaknesses

  Venice CPU production is expected to be slower than previously forecast.

  Comparison

  AMD AI GPU production is expected to use TSMC CoWoS, while non-TSMC suppliers mainly support Venice, high-end PC CPUs and gaming GPUs.

  Risks

  Slower ASE and Amkor capacity ramps could constrain Venice and require additional TSMC capacity.

• Broadcom Inc.

  ASIC ecosystem beneficiary linked to expanding AI-lab and TPU demand

  Strengths

  FY27 revenue guidance is US$115bn and could double again in FY28, according to the cited Morgan Stanley report.

  Comparison

  A Broadcom-supported US AI lab is expected to book roughly 15k-30k CoWoS wafers in 2027.

• MediaTek

  Potential ASIC design and packaging-demand beneficiary

  Strengths

  Morgan Stanley sees a growing chance of a second AI CSP or AI-lab customer through Nvidia NVLink Fusion.

  Comparison

  MediaTek/Google Humufish is expected to consume most relevant Intel EMIB-T capacity in 2027-28.

  Risks

  The potential customer decision remains uncertain.

Key data

• CSP capex growth12% into 2028Morgan Stanley US internet research estimate referenced in the report.
• Aggregate 2.5D packaging capacity growth50% in 2028The report’s preliminary CoWoS, CoPoS and EMIB-T capacity outlook.
• TSMC CoWoS capacity260kwpm in 2028Up from 130kwpm in 2026 and 200kwpm in 2027.
• Non-TSMC CoWoS capacity110kwpm by end-2028Up from 80kwpm at end-2027.
• Intel EMIB-T capacity40-45kwpm in 2028Projected from around 5kwpm in 2026 and 15-20kwpm in 2027.
• Global CoWoS demand2,509k wafers in 2027Up from 1,394k wafers in 2026.
• AI HBM consumptionUp to 44bn Gb in 2027Compared with up to 29bn Gb in 2026.
• AI wafer consumptionAt least US$55bn in 2027Compared with at least US$27bn in 2026.
• AMD 2027 CoWoS consumption345k wafersA 165% year-on-year increase in Morgan Stanley’s estimate.

Impact & implications

The report argues that advanced packaging is a key bottleneck and growth driver for the AI semiconductor supply chain. Continued expansion in CoWoS, CoPoS and EMIB-T supports the outlook for AI compute, ASICs, HBM and foundry demand, while delayed OSAT ramps may redistribute demand toward TSMC and constrain some AMD Venice production.

Risks

• CoPoS capacity expansion depends on successful TSMC trial production.
• ASE and Amkor CoWoS capacity ramps are slower than Morgan Stanley’s initial expectations.
• Slower OSAT expansion could constrain AMD Venice CPU production and divert TSMC capacity from AI GPUs.
• Intel EMIB-T output assumptions depend on supply-chain execution.

What to watch

• Progress of TSMC’s CoPoS trial production and subsequent capacity-build decisions.
• ASE, SPIL and Amkor CoWoS expansion versus customer forecasts.
• A potential MediaTek second AI CSP or AI-lab customer decision in 4Q26.
• CoWoS bookings from a Broadcom-supported US AI lab and demand for Microsoft Maia 200.
• GB200/GB300 rack output and resulting Blackwell GPU consumption.