AI semiconductor supply chain Report Interpretation

Overview

Morgan Stanley examines whether AI semiconductor growth can remain strong in 2028 as its US internet research expects CSP capex growth of 12%. Based on supply-chain checks and preliminary advanced-packaging assumptions, it concludes that compute-chip spending should outgrow overall AI capex, supported by larger chip sizes and broader use of 2.5D packaging across GPUs, XPUs, CPUs and networking.

Core views

Morgan Stanley argues that AI semiconductor capex, particularly compute-chip spending, should outgrow broader AI capex in 2028. Its starting point is an expected 12% increase in CSP capex into 2028, which has raised concerns over slowing AI semiconductor momentum. The report counters that preliminary CoWoS, CoPoS and EMIB-T capacity assumptions point to 50% aggregate 2.5D-packaging capacity growth in 2028. This capacity growth implies relatively flat infrastructure spending, including shell and AI data-center spending, and moderate memory pricing, while chip content continues to expand through larger dies and the use of advanced packaging for GPUs, XPUs, CPUs and networking. For TSMC, the report forecasts CoWoS capacity rising from 130kwpm in 2026 and 200kwpm in 2027 to 260kwpm in 2028. The 2028 expansion is expected to concentrate in Arizona AP9/10 and potentially AP7. TSMC is conducting CoPoS trial production in Taoyuan; if trials progress well, the report expects capacity construction at AP9/10 or AP7P3, reaching 5-10kwpm in 2028 and 10-20kwpm in 2029. Outside TSMC, Morgan Stanley expects combined ASE/SPIL and Amkor CoWoS capacity to rise from 80kwpm at end-2027 to 110kwpm by end-2028. ASE/SPIL is projected to expand FoCoS plus CoWoS from 30kwpm to 50-60kwpm, while Amkor could rise from 30kwpm to 55-60kwpm, with both emphasizing CoWoS-L and CoWoS-R. Intel is another source of future 2.5D capacity. The report estimates average EMIB-M capacity of 110kwpm currently, falling to 95kwpm in 2027 as capacity is converted toward EMIB-T. EMIB-T is projected to grow from about 5kwpm in 2026 to 15-20kwpm in 2027 and 40-45kwpm in 2028, equivalent to at least 2mn Humufish substrates and a 10-15% share of 2.5D packaging. Morgan Stanley believes MediaTek/Google Humufish will consume most EMIB-T capacity in 2027-28 and estimates Intel could produce close to 3mn Humufish units from late 2027 through 2028, assuming four to five EMIB-T chips per wafer. The report's demand analysis points to sharp growth in CoWoS consumption. Total global demand is forecast to rise from 1,394k wafers in 2026 to 2,509k in 2027, with total demand growth of 102% in 2026 and 80% in 2027. AMD's CoWoS demand is expected to climb 165% year-on-year to 345k wafers in 2027. TSMC CoWoS-L bookings for AMD are estimated to increase 200% year-on-year to 210k, led by MI455 and MI450, which could each reach roughly 500-650k units. However, slower-than-expected OSAT capacity expansion means TSMC may need to support around 80k CoWoS-L wafers for Venice CPU production, partly displacing AI GPU capacity. Morgan Stanley therefore lowers projected Venice CPU output to 4.4mn units from its initial 5.6mn forecast, even as Venice CoWoS bookings rise from 50k in 2026 to 210k in 2027. ASIC demand provides additional support. Broadcom's FY27 revenue guidance is US$115bn and could double again in FY28, according to a cited Morgan Stanley report; the supply-chain checks indicate an AVGO AI-lab customer could book approximately 15k-30k CoWoS wafers in 2027. Qualcomm's announced AWS ASIC partnership is viewed as having limited impact on Alchip because the release concerns inference, whereas Alchip's Trainium4 exposure spans training and inference. Morgan Stanley also sees a growing chance that MediaTek wins a second AI CSP or AI-lab customer through Nvidia NVLink Fusion, with a potential decision in 4Q26 serving as a significant catalyst. The report translates packaging allocations into broader semiconductor demand. It estimates AI HBM consumption of up to 29bn Gb in 2026 and 44bn Gb in 2027. AI wafer consumption is estimated at at least US$27bn in 2026 and at least US$55bn in 2027. It also notes August recovery in GB200 and GB300 NVL72 rack shipments, with a CY26 full-year forecast of 80-85k racks, which it reads as evidence of greater Blackwell GPU consumption. Across the supply chain, the report expects AI chip revenue to continue increasing sequentially and estimates TSMC's AI-related revenue could deliver a 60% CAGR from 2024 to 2029.

Analysis framework

Morgan Stanley combines Asian supply-chain checks with capacity forecasts for CoWoS, CoPoS and EMIB-T, then compares the resulting packaging and wafer requirements with CSP capex projections. It maps capacity allocations to specific AI GPU, CPU and ASIC programs to estimate chip shipments, HBM demand, wafer consumption and revenue opportunity.

Methodology notes

• Industry AnalysisSupply-demand framework

  Advanced-packaging supply-demand analysis

  The report forecasts capacity by packaging technology and supplier, then compares it with customer bookings and expected chip programs to assess bottlenecks, allocation changes and semiconductor demand.

• Industry AnalysisUpstream-Midstream-Downstream Transmission

  AI infrastructure spending transmission through the semiconductor supply chain

  The analysis links CSP capex and rack shipments to GPU and ASIC demand, advanced packaging, HBM consumption and wafer revenue.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• TSMC

  Primary advanced-packaging supplier supporting AI GPU, CPU and ASIC demand

  Strengths

  CoWoS capacity is forecast to reach 260kwpm in 2028; CoPoS trials could create additional capacity.

  Weaknesses

  May need to absorb Venice CPU demand when OSAT ramps lag, partly squeezing AI GPU capacity.

  Comparison

  Expected to retain substantially greater CoWoS capacity than the combined ASE/SPIL and Amkor base.

  Risks

  CoPoS expansion depends on successful trial production.

• Intel

  EMIB-T advanced-packaging supplier for large AI chips

  Strengths

  EMIB-T capacity is projected to reach 40-45kwpm in 2028 and can support larger chips with more reticles.

  Weaknesses

  EMIB-M capacity is expected to decline as capacity is converted to EMIB-T.

  Comparison

  EMIB-T capacity is converted into 12-inch CoWoS-wafer equivalents for comparison with TSMC.

  Risks

  The ability to support larger chips depends on supply-chain execution.

• AMD

  Major CoWoS demand driver through AI GPUs and Venice CPUs

  Strengths

  Total 2027 CoWoS consumption is expected to rise 165% year-on-year to 345k wafers.

  Weaknesses

  Venice CPU output is projected at 4.4mn units, below the initial 5.6mn forecast.

  Comparison

  AI GPU production is expected to use TSMC CoWoS, while non-TSMC suppliers are intended to support Venice CPU and other products.

  Risks

  Slower OSAT capacity ramps may constrain Venice production and require TSMC capacity.

• MediaTek

  Potential ASIC design beneficiary through Nvidia NVLink Fusion and Humufish demand

  Strengths

  Morgan Stanley sees a growing chance of a second AI CSP or AI-lab customer.

  Comparison

  MediaTek/Google Humufish is expected to consume most Intel EMIB-T capacity during 2027-28.

  Risks

  The potential customer decision is not yet confirmed.

Key data

• CSP capex growth into 202812%Morgan Stanley US internet research estimate
• Aggregate 2.5D packaging capacity growth in 202850%Preliminary CoWoS, CoPoS and EMIB-T capacity assumptions
• TSMC CoWoS capacity260kwpm in 2028Versus 130kwpm in 2026 and 200kwpm in 2027
• Non-TSMC CoWoS capacity110kwpm by end-2028Versus 80kwpm by end-2027
• Intel EMIB-T capacity40-45kwpm in 2028Versus about 5kwpm in 2026 and 15-20kwpm in 2027
• Global CoWoS demand2,509k wafers in 2027Versus 1,394k wafers in 2026
• AI HBM consumptionUp to 44bn Gb in 2027Versus up to 29bn Gb in 2026
• AI wafer consumptionAt least US$55bn in 2027Versus at least US$27bn in 2026

Impact & implications

The report sees advanced packaging as a key mechanism through which AI compute demand can continue to grow faster than overall CSP capex. TSMC, OSATs and Intel are positioned as capacity providers, while GPU and ASIC programs drive allocations; constrained or delayed OSAT ramps can redirect demand to TSMC and alter individual product-volume expectations.

Risks

• TSMC CoPoS capacity construction depends on successful trial production.
• Slower OSAT capacity ramps and lower panel-level packaging yields can constrain Venice CPU production.
• Intel's ability to support larger EMIB chips depends on supply-chain execution.

What to watch

• Progress of TSMC's CoPoS trial production and subsequent capacity-build decisions.
• Whether MediaTek wins a second AI CSP or AI-lab customer through Nvidia NVLink Fusion, potentially in 4Q26.
• The pace of ASE/SPIL and Amkor CoWoS capacity expansion.
• AI-lab ASIC CoWoS bookings supported by Broadcom.
• GB200/GB300 rack shipments as an indicator of Blackwell GPU consumption.