Morgan Stanley expects AI semiconductor spending to outgrow CSP capex again in 2028

Overview

Morgan Stanley examines whether AI semiconductor growth can remain strong in 2028 as CSP capex growth moderates. Its supply-chain checks indicate that compute-chip and advanced-packaging demand should continue to outpace broader AI infrastructure spending, driven by larger chips and expanding AI applications.

Core views

Morgan Stanley’s central conclusion is that AI semiconductor capex—particularly compute chips—should outgrow total AI capex in 2028. While Morgan Stanley’s US internet research projects 12% CSP capex growth into 2028, the Asia-Pacific technology team’s supply-chain checks support preliminary assumptions for 50% aggregate growth in 2.5D packaging capacity. The report argues that the divergence is possible because infrastructure spending such as data-center shells may be broadly flat and memory pricing only moderate, while AI compute intensity continues to rise. The capacity case rests on the growing use of 2.5D packaging for AI GPUs, XPUs, CPUs and networking chips. TSMC’s CoWoS capacity is expected to rise from 130kwpm in 2026 and 200kwpm in 2027 to 260kwpm in 2028, with expansion focused on Arizona AP9/10 and potentially AP7. The report expects TSMC to begin building CoPoS capacity after trial production in Taoyuan if progress is satisfactory, forecasting 5-10kwpm in 2028 and 10-20kwpm in 2029. Non-TSMC providers are projected to expand CoWoS capacity from 80kwpm at end-2027 to 110kwpm at end-2028, led by ASE/SPIL at 50-60kwpm and Amkor at 55-60kwpm. Intel is another component of the capacity outlook. Morgan Stanley expects EMIB-M capacity to decline from a current average of 110kwpm to 95kwpm in 2027 as capacity is converted to EMIB-T. EMIB-T is projected to rise from about 5kwpm in 2026 to 15-20kwpm in 2027 and 40-45kwpm in 2028. The report estimates this capacity could support close to 3mn MediaTek/Google Humufish units from late 2027 through 2028, assuming four to five chips per wafer. It notes that EMIB-T can support larger chips with more than 12 reticles if the supply chain executes well. The report cross-checks its outlook against ASIC developments. Broadcom’s FY27 revenue guidance of US$115bn could double again in FY28, and Morgan Stanley’s checks indicate a Broadcom-supported AI-lab customer may book roughly 15k-30k CoWoS wafers in 2027. Qualcomm’s announced AWS ASIC partnership is viewed as having limited impact on Alchip because the announced use case is inference, whereas Alchip’s Trainium4 exposure spans training and inference. Morgan Stanley also sees an increasing chance that MediaTek wins a second AI CSP or AI-lab customer through Nvidia NVLink Fusion; a decision in 4Q26 could be a significant catalyst. For 2027 demand, Morgan Stanley estimates global CoWoS consumption rising 80% year on year to 2,509k wafers, following estimated 102% growth in 2026. AMD’s CoWoS demand is forecast to rise 165% year on year to 345k wafers in 2027. The report expects MI455 and MI450 production of roughly 500-650k units each, with TSMC CoWoS-L bookings rising 200% year on year to 210k. However, slower-than-expected ASE and Amkor capacity ramps lead Morgan Stanley to lower its Venice CPU production estimate to 4.4mn units from its prior 5.6mn estimate; TSMC may need to supply around 80k CoWoS-L wafers for Venice, partly displacing AI GPU capacity. Morgan Stanley also identifies rising custom-chip demand. Microsoft Maia 200 bookings are estimated to increase from 1k CoWoS wafers in 2026 to 5k in 2027, implying roughly 100-150k chips. The report estimates AI HBM consumption could reach up to 44bn Gb in 2027, versus up to 29bn Gb in 2026, and AI wafer consumption could exceed US$55bn in 2027, compared with at least US$27bn in 2026. The report further points to an August recovery in GB200/GB300 NVL72 rack shipments and a CY26 full-year forecast of 80-85k racks as evidence of stronger Blackwell GPU consumption.

Analysis framework

Morgan Stanley combines Asian supply-chain checks with capacity plans, wafer-equivalent conversions, product-level shipment assumptions, cloud-capex tracking, and cross-checks against ASIC guidance and rack shipments. It translates advanced-packaging allocations into chip volumes, HBM demand and wafer-revenue estimates to assess the scale and timing of AI semiconductor demand.

Methodology notes

• Industry AnalysisSupply-demand framework

  Advanced-packaging capacity and AI-chip demand analysis

  The report compares projected CoWoS, CoPoS and EMIB-T capacity with expected chip demand to assess whether packaging supply can support AI semiconductor growth.

• Competition & strategyValue chain analysis

  AI semiconductor supply-chain mapping

  The report follows demand from cloud providers and AI labs through chip designers, foundries, packaging firms, memory suppliers and rack production.

• Industry AnalysisVolume-price decomposition

  Wafer-consumption and revenue estimation

  Morgan Stanley converts assumed packaging allocations and chips per wafer into wafer demand and estimated AI wafer revenue.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• TSMC

  Expected to remain the central provider of CoWoS capacity for AI GPUs and other AI chips.

  Strengths

  CoWoS capacity is forecast to reach 260kwpm in 2028, with potential CoPoS expansion.

  Weaknesses

  May need to allocate capacity to support Venice CPU production, partly squeezing AI GPU capacity.

  Comparison

  Expected 2028 CoWoS capacity exceeds the combined 110kwpm projected for OSAT providers.

  Risks

  CoPoS expansion depends on successful trial production.

• Intel

  EMIB-T capacity expansion supports large AI-chip packaging and Humufish production.

  Strengths

  EMIB-T could reach 40-45kwpm in 2028 and support larger chips with more than 12 reticles.

  Weaknesses

  EMIB-M capacity is expected to decline as capacity converts to EMIB-T.

  Comparison

  Capacity is converted into 12-inch CoWoS wafer equivalents for comparison with TSMC.

  Risks

  The larger-chip opportunity depends on supply-chain execution.

• AMD

  A major projected source of 2027 CoWoS demand through MI-series GPUs and Venice CPUs.

  Strengths

  Total 2027 CoWoS consumption is forecast to rise 165% year on year to 345k wafers.

  Weaknesses

  Venice CPU production is estimated at 4.4mn units, below Morgan Stanley’s prior 5.6mn forecast.

  Comparison

  AI GPU-related production is expected to be handled by TSMC, while OSAT providers focus on CPUs and gaming GPUs.

  Risks

  Slower-than-expected OSAT capacity ramps may constrain Venice production.

• Broadcom

  ASIC guidance and potential AI-lab orders provide a cross-check for custom AI-chip demand.

  Strengths

  FY27 revenue guidance is US$115bn and could double again in FY28 according to cited Morgan Stanley research.

  Comparison

  Broadcom-supported AI-lab demand could represent 15k-30k CoWoS wafers in 2027.

• MediaTek

  Potential beneficiary of further AI ASIC customer wins through Nvidia NVLink Fusion.

  Strengths

  Morgan Stanley sees a growing chance of a second AI CSP or AI-lab customer.

  Comparison

  MediaTek/Google Humufish is expected to consume most Intel EMIB-T capacity during 2027-28.

  Risks

  The prospective customer decision remains uncertain.

Key data

• CSP capex growth12%Morgan Stanley US internet research forecast into 2028
• Aggregate 2.5D packaging capacity growth50%Morgan Stanley’s preliminary 2028 forecast
• TSMC CoWoS capacity260kwpm2028 forecast, versus 130kwpm in 2026 and 200kwpm in 2027
• Non-TSMC CoWoS capacity110kwpmExpected by end-2028, versus 80kwpm at end-2027
• Intel EMIB-T capacity40-45kwpm2028 forecast, versus around 5kwpm in 2026
• Global CoWoS demand2,509k wafers2027 estimate, up 80% year on year
• AI HBM consumptionUp to 44bn Gb2027 estimate
• AI wafer consumptionAt least US$55bn2027 estimate

Impact & implications

The report argues that a moderation in aggregate CSP capex need not imply weaker AI semiconductor demand. Its projected growth in advanced packaging, AI wafer consumption and HBM demand suggests continued support for the AI compute supply chain, although bottlenecks or slower ramps at packaging providers can alter product allocation and shipment volumes.

Risks

• TSMC CoPoS capacity expansion depends on successful trial production.
• Intel’s ability to support larger EMIB-T chips depends on supply-chain execution.
• Slower-than-expected capacity ramps at ASE and Amkor could limit Venice CPU production and shift demand to TSMC.

What to watch

• Progress of TSMC’s CoPoS trial production and subsequent capacity-build decisions.
• 4Q26 developments on a potential second AI CSP or AI-lab customer for MediaTek.
• OSAT CoWoS capacity ramps and their effect on AMD Venice CPU production.
• AI-lab ASIC orders supported by Broadcom and their 2027 CoWoS bookings.
• GB200/GB300 rack shipments as an indicator of Blackwell GPU consumption.