China semiconductors and the LogicFolding advanced-logic supply chain Report Interpretation

Overview

Bernstein examines Huawei’s Kirin 9050 Pro, the first commercially shipped LogicFolding chip in the Mate XT2 tri-fold smartphone. It argues that the technology materially improves performance and efficiency from a 7nm-class DUV manufacturing base, with positive implications for China’s advanced-logic and advanced-packaging supply chain.

Core views

Huawei launched the second-generation Mate XT2 tri-fold smartphone on 7 September 2026 with the Kirin 9050 Pro, which Bernstein describes as the first commercially shipped LogicFolding chip. The institution’s central conclusion is that Huawei has achieved 3nm-class overall performance from a 7nm-class SMIC process using DUV lithography rather than EUV. Bernstein characterizes this as an underestimated architectural and manufacturing breakthrough, narrowing Huawei’s performance gap with Apple to about three years from roughly four years in the prior generation. The report distinguishes multicore and real-device performance from single-core transistor performance. Using Geekbench 6 as its primary cross-platform comparison, Bernstein says Kirin 9050 Pro’s multicore result exceeds Apple’s A17 Pro and Qualcomm’s Snapdragon 8 Gen 3, while its single-core result remains around the level of Snapdragon 8 Gen 2, Dimensity 9200 and Apple A14. In Geekbench 7 testing, Kirin 9050 Pro scored 1,813 single-core and 8,159 multicore, versus 1,596 and 6,802 for Kirin 9030 Pro, increases of 14% and 20%, respectively. Bernstein attributes the stronger multicore outcome to a nine-core, 16-thread design and HarmonyOS scheduling that better distributes work across cores. Bernstein also emphasizes real-world software-and-hardware co-optimization. In three 30-minute native HarmonyOS game tests on comparable tri-fold handsets, Mate XT2 broadly matched Samsung’s Galaxy Z TriFold with Snapdragon 8 Elite. In Genshin Impact, Huawei delivered 59.4 FPS against Samsung’s 59.8 FPS while rendering at 1920x1346 rather than 1518x966; its lowest 1% frame rate was 52.7 versus 46.9. The report notes that Mate XT2 used more power in Ananta and Wuthering Waves, at 6.4W versus 6.0W and 6.9W versus 6.2W, respectively. It also cautions that the gaming uplift versus Mate XTs—about 70% to 100%—cannot be apportioned among HarmonyOS 7, the Maleoon 955 GPU and LogicFolding. The underlying mechanism is LogicFolding, Huawei’s circuit-level implementation of its Tau-law approach. By stacking dies and shortening communication paths, the design creates timing headroom that can be used to reduce voltage and power at matched output or to raise clocks in turbo operation. Huawei’s roadmap cited by Bernstein shows transistor density increasing from 155 to 238 MTr/mm², or 55%. At equivalent performance versus Kirin 9030 Pro, Huawei laboratory results show power reductions of 66% for the NPU, 58% for the GPU and 41% for the CPU P-core; Geekbench 6 CPU power at the same 2.75GHz clock was down 23%. The smaller P-core gain reflects the fact that a single thread remains constrained to one pipeline, whereas GPU and NPU workloads can exploit additional parallel hardware. On measured block performance, the report states that Kirin 9050 Pro’s GPU scored 1,378 in Steel Nomad Light, up 39% from 993 for Kirin 9030 Pro, while peak single-precision throughput rose from 1.4 to about 2.2 trillion operations per second, up 57%. NPU INT8 throughput increased to 67.7 TFLOPS from 27 TFLOPS, a 150% gain. The NPU is described as capable of running a 30-billion-parameter mixture-of-experts model locally, with about 2 billion parameters active per step. Bernstein notes a technical exception in DSP: power fell 25%, but area declined 40%, raising power density 24%; Huawei claims 2027 silicon will bring its heat density below the unstacked predecessor. For the supply chain, Bernstein argues that the launch signals substantial upside for Chinese advanced-logic and advanced-packaging demand. It believes SMIC manufactures the chip on a 7nm DUV process and should be the major beneficiary, as each Kirin 9050 Pro requires twice the logic-wafer consumption of a planar Kirin 9030 Pro. NAURA is identified as a major supplier of etch and deposition equipment for SMIC’s 7nm process, while Piotech is identified as a domestic leader in wafer-to-wafer bonding tools that could benefit as LogicFolding adoption expands beyond Huawei. The report rates all three Outperform. Remaining uncertainties are manufacturing cost and available capacity for wider adoption, while the technology is currently proprietary to Huawei.

Analysis framework

Bernstein combines Huawei disclosures and laboratory material with third-party Geekerwan testing. It compares matched-clock power, single-core and multicore benchmarks, GPU and NPU tests, and real-device gaming results, then links the technology’s expected wafer, equipment and bonding-tool demand to covered domestic suppliers.

Methodology notes

• Industry AnalysisUpstream-Midstream-Downstream Transmission

  Advanced-logic and packaging supply-chain transmission

  The report links Huawei’s chip architecture to higher logic-wafer use at SMIC and to demand for NAURA’s process tools and Piotech’s bonding equipment.

• Other

  Matched-clock and cross-platform benchmark comparison

  Bernstein uses Geekbench, SPEC CPU, GPU, NPU and gaming tests to compare performance and power under similar conditions, while noting benchmark limitations.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• SMIC (981.HK; 688981.CH)

  Bernstein believes SMIC manufactures Kirin 9050 Pro on a 7nm DUV process and should benefit most from rising LogicFolding demand.

  Strengths

  Potentially higher logic-wafer demand; each Kirin 9050 Pro is estimated to use twice the logic wafers of planar Kirin 9030 Pro.

  Risks

  Manufacturing cost and available capacity remain uncertainties for wide adoption.

• NAURA (002371.CH)

  Major supplier of etch and deposition equipment for SMIC’s 7nm process.

  Strengths

  Could benefit from higher advanced-logic process demand.

  Risks

  Benefit depends on sustained demand and manufacturing expansion.

• Piotech (688072.CH)

  Domestic leader in wafer-to-wafer bonding tools for advanced packaging.

  Strengths

  Could benefit if LogicFolding adoption broadens.

  Risks

  Technology is currently proprietary to Huawei and broader adoption is not yet established.

Key data

• Mate XT2 launch7 September 2026Huawei’s second-generation tri-fold smartphone launched with Kirin 9050 Pro.
• Mate XT2 starting priceRMB19,999General sales were scheduled to begin on 12 September 2026.
• Geekbench 7 score1,813 single-core / 8,159 multicoreVersus 1,596 / 6,802 for Kirin 9030 Pro; increases of 14% and 20%.
• GPU performance1,378 versus 993Steel Nomad Light score, a 39% increase versus Kirin 9030 Pro.
• NPU INT8 throughput67.7 TFLOPS versus 27 TFLOPSA 150% increase versus Kirin 9030 Pro.
• Iso-performance power reduction66% NPU, 58% GPU, 41% P-coreHuawei laboratory comparison versus Kirin 9030 Pro.
• Logic-wafer consumption2xBernstein estimates each Kirin 9050 Pro doubles logic-wafer consumption versus planar Kirin 9030 Pro.

Impact & implications

Bernstein believes LogicFolding could expand domestic demand for 7nm-class advanced logic and advanced packaging even without EUV access. It identifies SMIC as the principal foundry beneficiary, NAURA as an equipment beneficiary and Piotech as a bonding-tool beneficiary if the ecosystem matures and other local fabless companies adopt the technology.

Risks

• Manufacturing cost and available manufacturing capacity are the remaining uncertainties for broad LogicFolding adoption.
• LogicFolding is currently proprietary to Huawei, and adoption by other local fabless companies depends on ecosystem maturity.
• The first-generation folded DSP has higher power density than the planar predecessor despite lower absolute power.