China AI infrastructure ecosystem Report Interpretation

Overview

This industry deep dive examines how rapidly rising Chinese AI inference demand could drive a broad domestic infrastructure buildout. JPMorgan’s central view is that localization will expand quickly and support multiple supply-chain segments, but limited advanced-foundry capacity, yield challenges and constrained HBM availability will restrain near-term chip supply and shape which companies benefit.

Core views

JPMorgan argues that China’s AI infrastructure cycle is being driven primarily by inference rather than training. The emergence of low-cost open-source models, including DeepSeek, helped daily token consumption rise from about 100 billion in early 2024 to more than 140 trillion by March 2026—an increase of more than 1,000 times in under two years. The report expects consumer and enterprise adoption, agentic AI, multimodal applications, longer contexts and repeated tool-calling to continue raising tokens per session. JPMorgan’s China Internet team forecasts token consumption at roughly 330% CAGR over 2025-30. The report converts that token outlook into infrastructure demand through an inference-throughput framework. It distinguishes compute-intensive prefill, which affects Time to First Token, from memory-intensive decode, which determines Time per Output Token; the latter requires greater memory capacity and bandwidth. Its assumptions include deployment of a 671-billion-parameter model, TPOT below 50ms, batch size of 128 and KV-cache length of 4,096. Under this approach, incremental inference compute demand grows at about 80% CAGR through 2030 and accounts for 85% of total compute requirements by then. AI-chip demand rises about 40% CAGR during 2026-30E to roughly 14 million units by 2030E, assuming single-die packages and steady performance gains. The model assumes throughput of 1 token/s per TFLOPS initially and about 30% annual efficiency gains to 3.3 by 2028E; optimization can ease demand but does not eliminate the supply constraint. Supply is the report’s principal limiting factor. JPMorgan estimates domestic AI-chip shipments of 2 million, 3 million and 5 million units in 2026E, 2027E and 2028E, respectively, and expects domestic localization to reach 80% of total supply by 2028E and 90% by 2030E as overseas GPU availability remains constrained. Local players target 150,000-200,000 wafers per month of advanced logic capacity over the next two to three years, but effective output depends on yield improvement and migration to more advanced nodes. The report therefore expects a seller’s market for domestic GPUs and ASICs over the next 6-12 months, favoring vendors with secured capacity or inventory. It also projects roughly RMB230 billion, RMB326 billion and RMB532 billion of AI server/hardware revenue in 2026E, 2027E and 2028E, while noting that approval to procure H200 or other overseas chips would add uncertainty. HBM is the second major bottleneck. Existing domestic chips predominantly use HBM2e, while the move to HBM3/HBM3e is constrained by qualification timing and equipment access. JPMorgan forecasts HBM demand at about 60% CAGR in 2026-30E and estimates about 200,000 wafers per month of HBM3e memory-die front-end capacity would be needed by 2030E to fully meet localized demand. It expects the HBM self-reliance gap to close only gradually because product competitiveness matters as much as capacity. The report also sees constraints in domestic chips’ lower-precision support, noting that many currently available products do not yet support FP8/FP4, which could weigh on model competitiveness and AI application adoption. JPMorgan sees advanced packaging, interconnects and system design as the practical route to improving usable performance under front-end restrictions. Chiplet and multi-die designs can use smaller dies to mitigate yield limits and improve output per wafer, increasing the importance of 2.5D/3D packaging and efficient die-to-die communication. Domestic OSATs can handle CoWoS-S-like solutions or a mix with CoWoS-R, but the transition toward CoWoS-L-like technology is expected from late 2026 or later and needs monitoring. The report highlights Huawei’s Tau Scaling and LogicFolding as examples of pursuing performance gains despite constrained geometric scaling: Kirin 2026’s two-tier LogicFolding is expected to lift transistor density to 238MTr/mm2, up 55% in one generation, and improve performance-core power efficiency by 41%. At the system level, the report argues that Chinese vendors can offset individual-chip gaps through workload specialization, high-density scale-up and software optimization. Huawei’s Ascend 950PR is designed for prefill and recommendation, while the 950DT uses higher memory capacity and bandwidth for decode and training; the latter offers up to 4TB/s bandwidth and 144GB memory. Huawei’s CloudMatrix384 combines 384 Ascend 910 chips and 192 Kunpeng CPUs into a system with more than 300 PFLOPS, while Alibaba’s Panjiu AL128 supports 128-144 GPUs and Sugon’s showcased supercluster uses 10,240 accelerator cards and claims more than 5 EFLOPS. These systems aim to reduce inefficiencies from scale-out networking, although they require heavy capital spending, higher power capacity and redesigned data centers. Proprietary toolkits such as Huawei CANN, Cambricon NeuWare, MetaX MXMACA and Moore Threads MUSA are intended to improve hardware utilization, but long-run adoption depends on framework compatibility and cost-performance. The report extends the thesis beyond semiconductors. AI servers and data centers raise rack-level power density, making liquid cooling increasingly necessary and driving demand for prefabricated power modules, 800V DC, solid-state transformers, backup power, ESS and smart-grid investment. JPMorgan forecasts incremental AI data-center power demand at about 50% CAGR during 2026-30E and expects data-center use to represent about 5% of China’s total power consumption by 2030E. It does not view aggregate Chinese power supply as a binding constraint, but sees a structural infrastructure cycle centered on thermal management, power architecture, storage and grid integration. JPMorgan identifies beneficiaries across the indigenous supply chain. It prefers AI-chip suppliers with inventory and leading-edge capacity, domestic WFE names, OSAT and test providers, server ODM/OEMs, and wholesale IDCs supported by AI cabinet demand and tighter power-quota screening. Named top picks include Iluvatar CoreX, NAURA, AMEC, JCET, V-Test, Huaqin, VNET, Sungrow, CATL and TGOOD. It remains Neutral on SMIC because low yields and rising depreciation pressure margins, and Underweight on Envicool following weak 1Q26 operating results, earnings cuts and a valuation gap relative to its implied global server-cooling share.

Analysis framework

JPMorgan starts with observed token growth and a forecast for inference usage, translates token throughput into computing and chip demand using model-serving assumptions, then tests that demand against foundry, packaging and HBM supply. It subsequently evaluates how multi-die packaging, supernodes, software stacks and power infrastructure can mitigate hardware limits, and maps the resulting demand across covered supply-chain companies.

Methodology notes

• Industry AnalysisSupply-demand framework

  AI-chip, foundry-capacity and HBM supply-demand analysis

  The report compares token-driven demand for compute, chips and HBM with accessible fabrication capacity, yields and qualification progress to identify likely bottlenecks and beneficiaries.

• Industry AnalysisUpstream-Midstream-Downstream Transmission

  AI infrastructure supply-chain mapping

  The analysis traces demand from AI chips and manufacturing equipment through packaging, servers and data centers to cooling, power, ESS and grid equipment.

• Industry AnalysisVolume-price decomposition

  Inference-throughput and chip-unit demand model

  The report translates token volume into compute throughput and then into chip-unit demand, while incorporating assumptions on hardware utilization, efficiency and package size.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• Iluvatar CoreX (9903 HK)

  Preferred domestic AI-chip supplier positioned to benefit from local chip demand and constrained overseas GPU access.

  Strengths

  JPMorgan cites product and supply-chain strategy, inventory and capacity support.

  Risks

  Foundry allocation, product performance, compatibility and cost efficiency remain important.

• NAURA (002371 CH)

  Preferred WFE beneficiary of advanced logic and memory capacity additions.

  Strengths

  Exposure to localization and higher-density capital spending.

  Risks

  Execution of domestic capacity additions and technology migration.

• AMEC (688012 CH)

  Preferred WFE beneficiary of upbeat demand for localized advanced manufacturing.

  Strengths

  Exposure to continuous advanced-logic and memory capacity additions.

  Risks

  Foundry-capacity expansion and yield progress.

• JCET (600584 CH)

  Covered OSAT beneficiary of rising advanced-packaging content.

  Strengths

  JPMorgan expects higher-value full-stack CoWoS-like packaging services and share gains.

  Weaknesses

  Transition to CoWoS-L-like technology remains uncertain.

  Risks

  Technology-transition progress and upstream wafer-out timing.

• V-Test (688372 CH)

  Covered testing provider benefiting from higher volumes and longer test times for high-end AI chips.

  Strengths

  Testing multiplier effect from inferior manufacturing yields and multi-chip packages.

  Risks

  Dependent on local foundry chip output.

• Huaqin (603296 CH)

  Preferred server ODM/OEM beneficiary of Superpod deployments and domestic server demand.

  Strengths

  Full-stack R&D and manufacturing across AI servers, general servers and high-speed switches.

  Risks

  Customer capex and deployment complexity.

• VNET (VNET US)

  Top IDC pick benefiting from AI-related orders and higher-power cabinet deployments.

  Strengths

  Management indicated more than 70% of current new orders are AI-related; pricing and margins may benefit from power-quota screening.

  Risks

  Domestic AI-chip supply constraints and lower-than-expected China CSP capex.

• Sungrow (300274 CH)

  ESS beneficiary of grid-friendly AI data-center power configurations.

  Strengths

  Management frames AIDCs as a new opportunity set for ESS.

  Risks

  Extent and pace of AIDC ESS adoption.

• CATL (3750 HK/300750 CH)

  Preferred battery-supply-chain beneficiary of AIDC energy-storage deployment.

  Strengths

  ESS cell and system technology, sodium-ion ESS, and a strategic VNET stake supporting a deployment channel.

  Risks

  Execution of targeted AIDC deployments and infrastructure investments.

• TGOOD (300001 CH)

  Preferred AI data-center power-equipment play.

  Strengths

  Exposure to high-voltage prefabricated infrastructure and AI Powerhouse modules intended to reduce delivery time, capex and power costs.

  Risks

  Adoption of 800V DC/SST and prefabricated power architectures.

Key data

• Daily token consumptionMore than 140 trillion by March 2026Up from about 100 billion in early 2024; more than 1,000x growth in under two years.
• China token-consumption forecast~330% CAGR, 2025-30JPMorgan China Internet team forecast, driven by greater adoption and agentic/multimodal use cases.
• Inference compute demand~80% CAGR through 2030Expected to represent 85% of total compute requirements by 2030.
• AI-chip demand~40% CAGR, 2026-30E; ~14 million units by 2030EBased on token-demand growth, single-die packages and assumed performance improvement.
• Domestic AI-chip supply2 million / 3 million / 5 million unitsJPMorgan estimates for 2026E / 2027E / 2028E.
• Advanced logic capacity addition target150,000-200,000 wafers per monthTargeted over the next two to three years, but yield and node-migration challenges limit effective output.
• HBM demand~60% CAGR, 2026-30EAbout 200,000 wafers per month of HBM3e memory-die capacity would be needed by 2030E to meet localized demand.
• Incremental AI data-center power demand~50% CAGR, 2026-30EData-center power consumption is projected to reach about 5% of China’s total by 2030E.

Impact & implications

The report’s central implication is that constrained access to overseas chips and limited domestic leading-edge supply should accelerate localization across China’s AI hardware ecosystem. It expects the strongest leverage among firms with secure capacity, inventory, advanced packaging or testing capabilities, and among suppliers enabling higher-density AI servers, data centers, cooling, power systems, ESS and grid integration.

Risks

• Advanced-foundry capacity, yields and technology migration may keep domestic AI-chip supply below demand.
• HBM3/HBM3e qualification and equipment-access constraints may delay self-reliance.
• Approval to procure H200 or other overseas chips could alter domestic hardware-demand assumptions.
• Supernode and cluster deployments require substantial capital spending, more power capacity and data-center redesign.
• Domestic AI-chip competitiveness depends on performance, compatibility, cost efficiency and software-framework support.
• Lower-than-expected China CSP capital expenditure could pressure data-center demand.

What to watch

• Progress in leading-edge foundry capacity allocation, yields and wafer-out from 2H26 onward.
• HBM3/HBM3e qualification, capacity development and domestic product competitiveness.
• The transition from CoWoS-S/R-like solutions toward CoWoS-L-like advanced packaging.
• CSP and enterprise capital spending, local-hardware adoption and customer satisfaction with localized chips.
• Adoption of FP8/FP4 support, software optimization and proprietary toolkit compatibility.
• AI-related data-center orders, power-quota policy, liquid-cooling uptake, and ESS/grid-infrastructure deployment.