Report Interpretation

Overview

Bernstein examines whether retired DDR4 memory connected through Compute Express Link can become CXL's first large-scale commercial application and a material new business for Montage Technology. It concludes that an emerging server-memory shortage, large cost savings and AI-driven demand for warm memory create a credible opportunity, while bandwidth, latency and qualification constraints limit adoption to suitable workloads.

Core views

Bernstein's central conclusion is that DDR4 reuse could move CXL from ecosystem development into meaningful commercial deployment and become a new growth engine for Montage. Agentic AI is increasing demand not only for accelerators but also for CPUs, execution environments and server DRAM. Hyperscalers are consequently looking for additional memory capacity, and Meta has already described a production CXL platform that reuses retired DDR4. Bernstein says discussions with Montage indicate that Chinese cloud service providers are developing similar solutions. Based on this opportunity, the institution reiterates Outperform, maintains target prices of HKD 520 for the H-share and CNY 400 for the A-share, and estimates potential incremental revenue equal to about 10% of its 2028E sales projection. CXL addresses a broader architectural problem known as the memory wall: processor capability and data-intensive workloads have grown faster than practical local-memory capacity, while memory can remain underused on one server and scarce on another. CXL 1.0 and 1.1, introduced in 2019 on top of the PCIe physical layer, established CXL.io, CXL.cache and CXL.mem. CXL 2.0 in 2020 added switching, memory pooling and formalized memory-expander controllers. CXL 3.0 in August 2022 doubled per-lane bandwidth to 32 GT/s and expanded fabric and sharing capabilities, while CXL 3.1 in 2024 refined latency and management features. The report distinguishes direct-attached expansion, which adds private memory to one host; switched pooling, which reallocates pooled capacity among hosts; and CXL Fabric or G-FAM, which could support shared memory across nodes. Direct expansion is the least complex and most commercially mature, while large-scale coherent sharing requires a longer hardware and software development path. The demand case begins with a widening server-memory imbalance. Bernstein forecasts server DDR demand to grow at a 47.3% CAGR over 2025-28E, driven by a 24% CAGR in server CPU shipments over 2025-30E and an 18% CAGR in DDR capacity per CPU. Memory capacity per CPU had already grown at a 17% CAGR during 2021-25. Against this demand, the report expects global DRAM bit capacity to expand by about 22% over 2026-28E; another exhibit estimates worldwide DRAM production at 73.6 billion GB in 2028, representing a 23.8% CAGR over 2025-28E. Supply additions take time to build, ramp and qualify, while HBM competes for manufacturing resources: Micron's disclosed comparison indicates that HBM3E requires about three times the wafer supply of DDR5 for an equivalent number of bits on the same process node. Bernstein therefore estimates a server DDR shortfall of approximately 5.5 billion GB in 2027E and 11 billion GB in 2028E and maintains a supply-constrained outlook despite expected expansion by Chinese producers. Retired DDR4 offers capacity before the modules reach the end of their useful lives. Meta cited a server replacement cycle of five to seven years against a DRAM lifetime of 10 to 14 years, suggesting that platform retirement can occur well before memory retirement. CXL allows a DDR5-generation CPU to access qualified retired DDR4 through an MXC, turning otherwise stranded modules into a warm-memory tier. Using August 2026 pricing, Bernstein estimates that DDR4 reuse can be 58-73% cheaper than equivalent native DDR5. Its detailed 128GB example assumes two reused 64GB DDR4 DIMMs with an aggregate opportunity cost of US$640, a US$30 MXC and roughly US$250 of other add-in-card cost. The resulting US$920 configuration compares with US$3,500 for native DDR5, saving US$2,580 or 74%. For 64GB, the reuse configuration costs US$620 and saves US$880, or 59%, against a US$1,500 DDR5 benchmark. The analysis uses indicative used-module ranges of US$156-181 for 32GB and US$288-352 for 64GB. Bernstein builds its market estimate from the server DDR supply-demand gap. It assumes CXL-enabled DDR4 reuse addresses 50% of that gap during 2028-30, calculates controller dollar content per GB from controller prices and supported capacity, and multiplies the addressed capacity by that dollar content. The detailed analysis produces a global DDR4-reuse MXC market of roughly US$8.2 billion in 2030E and total CXL-chip market potential across use cases of US$9.9 billion in 2030. Assuming Montage captures 50% of China and 10% of markets outside China, Bernstein derives incremental revenue equivalent to roughly 10% of its 2028E sales estimate. Montage is positioned as the only meaningful domestic merchant MXC supplier in China and already has relationships across the server-memory-interface supply chain. Its M88MX5891 uses PCIe 5.0 x8/CXL 2.0, one DDR4 channel and two DIMMs per channel. That configuration supports smaller, lower-cost capacity increments than 12-DIMM systems from Astera Labs and Marvell. Astera's Leo 2 DDR4 configuration and Marvell's Structera X2404 use four channels and can support up to 12 DIMMs and about 1,536GB in the illustrated configurations, whereas Montage's design supports two DIMMs and a typical 64GB, 128GB or 256GB increment depending on DIMM density. Meta's production Vistara implementation provides operational validation through a system with 768GB of local memory and 256GB of CXL memory using two custom ASICs, although Meta's captive design is not a merchant competitor. Montage's simpler architecture is suited to economical warm-capacity additions, but revenue conversion still depends on cloud-provider qualification, card deployment and competitive share. Technical feasibility is strongest in general-purpose servers. Such CPUs commonly provide roughly 80-128 PCIe lanes, making it more manageable to assign x8-x16 lanes to one or two MXCs than in accelerator-heavy AI servers, where GPUs, networking and storage consume more I/O. Bernstein's illustration assumes other required I/O uses 40 lanes: an 80-lane CPU would retain 40 lanes before CXL and 24 after installing two x8 MXCs, while a 128-lane CPU would retain 88 and then 72 lanes. Nominal lane availability is not sufficient by itself, however, because motherboard routing, CXL-capable ports, firmware, supported device counts and platform qualification determine whether the capacity can actually be deployed. Bandwidth and latency constrain which workloads can use the recycled memory. PCIe 5.0 x8 offers a theoretical 31.5GB/s in each direction before protocol overhead, compared with 25.6GB/s for a single DDR4-3200 channel. Montage's single-channel design is therefore limited downstream by DDR4 bandwidth, while larger multi-channel systems can instead become limited by the host link. A single Montage expander is broadly comparable with one native DDR4 channel, not a CPU's full multi-channel local-memory subsystem. Latency is more consequential: Bernstein uses a low-load reference range of approximately 200-270ns for selected direct-attached CXL ASIC implementations, roughly two to 2.5 times local DRAM, with published reference points of 214ns, 239ns and 271ns. Queuing can worsen latency as utilization approaches the capacity of the host link or DDR interface. For this reason, Bernstein does not assume CXL reuse can satisfy the entire server DDR shortfall. The best-fit workloads combine a large resident-memory requirement with a relatively small hot working set. Local DDR retains frequently accessed data, while CXL DDR4 holds warmer pages that benefit from memory addressing but do not need native-DRAM performance. Meta's prior memory-offloading work reported memory savings of 20-32%, supporting the existence of tiering opportunities. Bernstein identifies agent sandboxes and virtual machines as the strongest case because many execution environments remain resident while waiting for models, tools or users. Inactive or reusable KV-cache blocks may also fit if retention saves enough recomputation and transfer time meets response targets. RAG and vector databases can place a long tail of vectors in CXL while keeping hot search structures local, although graph traversal and random access make tail latency important. Recommendation and embedding tables offer a similar hot-cold split, but only where access concentration is sufficiently stable. CXL DDR4 is therefore a warm-memory tier, not a wholesale replacement for DDR5. The initial reuse cycle may also accelerate broader CXL adoption by improving hardware qualification, software maturity and cloud-provider familiarity. Later opportunities include pooling memory across hosts to reduce stranded capacity and, over a longer horizon, sharing memory to reduce duplication and data movement. Bernstein updates its company and industry models accordingly: 2027E and 2028E EPS are raised by 2% and 11%, and the forecast table shows 2028E revenue of RMB27.936 billion, 10.3% above the previous estimate. Forecast revenue is RMB7.059 billion in 2026E, RMB14.030 billion in 2027E, RMB27.936 billion in 2028E, RMB47.739 billion in 2029E and RMB69.520 billion in 2030E. The corresponding basic EPS forecasts are CNY3.44, CNY5.69, CNY11.74, CNY20.03 and CNY28.44. The update page says the A-share 2BF P/E was cut to 47x, while the valuation section states that the CNY400 A-share target is based on 51x 2BF P/E. The HKD520 H-share target represents a 15% premium to the A-share target using a CNY/HKD rate of 1:1.13 and implies 59x 2BF EPS; Bernstein attributes the premium to Montage's scarcity as a China AI-exposed company without the direct geopolitical restrictions faced by some Chinese semiconductor peers.

Analysis framework

Bernstein first explains how CXL evolved and separates direct expansion, pooling and sharing. It then forecasts server-memory demand and supply to quantify the expected shortage, tests the economics of using retired DDR4 instead of native DDR5, and converts the addressable capacity gap into an MXC market estimate. The report compares available controller architectures, examines PCIe-lane, bandwidth and latency constraints, classifies workloads by memory capacity and access sensitivity, and finally incorporates the estimated opportunity into Montage's earnings model and P/E-based target prices.

Methodology notes

• Industry AnalysisSupply-demand framework

  Server DDR supply-demand gap

  The report forecasts server DDR demand from CPU shipments and memory per CPU, compares it with DRAM bit-capacity growth and product-allocation constraints, and uses the resulting shortage to establish the need for recycled DDR4.

• Industry AnalysisVolume-price decomposition

  Bottom-up CXL MXC TAM calculation

  Bernstein assumes DDR4 reuse addresses 50% of the projected capacity gap in 2028-30 and multiplies that capacity by estimated MXC dollar content per GB to derive annual controller revenue potential.

• Industry Analysis

  Workload capacity-versus-access-sensitivity framework

  The report evaluates workloads on two dimensions: total memory capacity required and sensitivity to bandwidth and latency. Workloads with large footprints but small hot working sets are considered the best candidates for a CXL warm-memory tier.

• Valuation methodsP/E and PEG Valuation

  Two-year-forward P/E target valuation

  The A-share target price is presented using a two-year-forward P/E framework, while the H-share target applies a premium to the A-share target and is also expressed as an implied forward P/E.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• Montage Technology (06809.HK; 688008.CH)

  Primary covered company and expected domestic beneficiary of CXL-enabled DDR4 reuse.

  Strengths

  Only meaningful domestic merchant MXC vendor identified in China, established server-memory-interface relationships and a simple low-cost architecture for smaller capacity increments.

  Weaknesses

  Its single DDR4 channel caps theoretical downstream bandwidth at 25.6GB/s, and commercial conversion still requires firmware, platform, software and cloud-provider qualification.

  Comparison

  The M88MX5891 supports two DDR4 DIMMs through PCIe 5.0 x8, providing a smaller deployment unit than the 12-DIMM, four-channel products described for Astera Labs and Marvell.

  Risks

  Lower memory or AI data-center server demand, intensifying competition and failure to introduce new AI data-center networking products.

• Astera Labs

  Merchant competitor in CXL memory-expander controllers.

  Strengths

  Leo 2 supports PCIe 6.0, four DDR channels and DDR4 configurations with up to 12 DIMMs.

  Weaknesses

  The expanded Leo 2 family was described as sampling with hyperscaler customers rather than as a broadly deployed production product.

  Comparison

  Offers larger capacity and more channels than Montage's simpler two-DIMM design.

• Marvell

  Merchant competitor in CXL memory-expander controllers.

  Strengths

  Structera X2404 supports four DDR4 channels and up to 12 DIMMs, providing as much as 1,536GB in the illustrated configuration.

  Weaknesses

  At three DIMMs per channel, the reported DDR4 speed falls to DDR4-1600, reducing aggregate downstream bandwidth.

  Comparison

  Targets a larger expansion subsystem than Montage's lower-cost incremental architecture.

• Meta Platforms (META)

  Operational example and captive CXL implementation rather than a merchant competitor.

  Strengths

  Its Vistara deployment provides production evidence that retired DDR4 can operate as a CXL warm-memory tier.

  Weaknesses

  The solution uses custom internal ASICs and is not merchant silicon.

  Comparison

  The production system combines 768GB of local memory with 256GB of CXL memory using two custom ASICs.

Key data

• DDR4-reuse CXL MXC TAMApproximately US$8.2bn by 2030EBottom-up estimate based on the server DDR shortfall and MXC dollar content per GB.
• Total CXL-chip TAMUS$9.9bn in 2030EIncludes DDR4 reuse and other CXL use cases.
• Montage market-share assumptions50% in China; 10% outside ChinaAssumptions used to estimate Montage's incremental revenue opportunity.
• Potential 2028 revenue upsideApproximately 10%Incremental potential relative to Bernstein's 2028E sales projection.
• Server DDR demand growth47.3% CAGR over 2025-28EDriven by more server CPUs and greater DDR capacity per CPU.
• Server CPU shipment growth24% CAGR over 2025-30EForecast supported by agentic-AI infrastructure demand.
• Projected server DDR shortfallApproximately 5.5bn GB in 2027E and 11bn GB in 2028EThe shortage underpins the case for alternative memory capacity.
• 128GB reuse economicsUS$920 versus US$3,500 for native DDR5Estimated saving of US$2,580, or 74%, including controller and card costs.
• CXL latency referenceApproximately 200-270nsIllustrative low-load range, roughly two to 2.5 times local DRAM.
• 2027E and 2028E EPS revisions+2% and +11%Model revisions after incorporating the CXL opportunity.
• 2028E revenue forecastRMB27.936bn10.3% above Bernstein's previous forecast.
• Target pricesHKD520 for H-share; CNY400 for A-shareBoth target prices are maintained.

Impact & implications

The report argues that DDR4 reuse can create a near-term commercial bridge between today's direct CXL expansion products and longer-term pooling and shared-memory architectures. For Montage, a qualified rollout by Chinese cloud providers could diversify growth beyond its core memory-interface business and lift 2028 revenue by about 10%, but the opportunity is limited to workloads that tolerate a slower warm-memory tier and depends on qualification, deployment and market share.

Risks

• A decrease in memory and AI data-center server demand could weaken Montage's growth outlook.
• Intensifying competition could lead to market-share loss and lower margins.
• Montage may fail to introduce new products for the AI data-center networking market.

What to watch

• Cloud-service-provider qualification, add-in-card deployments and Montage's realized competitive share will determine how much of the estimated opportunity converts into revenue.
• Monitor whether motherboard routing, firmware and usable CXL-capable ports allow nominal PCIe lane headroom to become deployable capacity.
• Track workload-level throughput and tail latency under concurrency, including traffic generated by migration between local and CXL memory tiers.
• Watch the health, remaining service life and platform compatibility of retired DDR4 modules.
• Assess progress from direct expansion toward memory pooling and shared-memory architectures, which require broader hardware and software maturity.