Tiered HBM Configurations and Rack Architecture Optimization Support AI Chip Volume Growth, While Power and Supernode Delivery Remain Core Constraints

Overview

This report focuses on GPU architecture, HBM configurations, supernode interconnects, ASIC projects, CoWoS capacity, and testing demand in the Asia-Pacific AI supply chain. The core view is that NVIDIA may ease memory shortages and cost pressure through tiered HBM configurations for Rubin Ultra, while continuing to increase rack-level GPU density and using CPO or NPO to support larger-scale interconnects. Google TPU and CPU demand, AI chip testing complexity, and advanced packaging demand continue to rise, but power supply, PCB and cooling, HBM capacity, and server rack delivery schedules may still limit actual volume ramp-up.

Core views

First, Rubin Ultra may come in multiple HBM configurations, with high-end models emphasizing performance and low-end models reducing memory capacity to fit different workloads and improve supply availability. Second, lower HBM specifications may have limited impact on prefill tasks but are more sensitive for decoding performance of long-context large models; meanwhile, lower per-chip memory capacity may increase chip demand. Third, Kyber blade servers still face PCB and cooling challenges, and first-generation Rubin Ultra racks may continue to use Oberon NVL72 and scale to the NVL576 level through CPO or NPO. Fourth, demand for Google TPU, CPU, and related burn-in and system-level testing is growing rapidly, benefiting segments such as MediaTek, GUC, and King Yuan Electronics Co Ltd. Fifth, CoWoS, HBM, and wafer demand are growing rapidly, but constraints have gradually expanded from pure chip manufacturing to power, cooling, interconnects, and full-system delivery.

Analysis framework

The report combines supply chain research, product specification breakdowns, CoWoS wafer allocation, chips per wafer, HBM capacity configurations, server-to-rack conversion relationships, and per-chip power consumption assumptions to estimate GPU and ASIC shipments, HBM consumption, wafer revenue opportunities, and power demand from the bottom up. It also assesses revenue contributions across each segment based on cloud customer project progress and testing requirements.

Methodology notes

• Supply Chain AnalysisSupply Chain Research and Cross-Validation

  Cross-validate product specifications and mass production schedules through information from multiple segments such as memory, packaging, testing, servers, and optical interconnects.

  This method is suitable for assessing Rubin Ultra HBM configurations, Kyber rack progress, and ASIC project division of labor that have not yet been finalized, but conclusions may still change with customers' final designs and mass production plans.

• Capacity AnalysisBottom-Up Capacity and Shipment Mapping

  Estimate GPU and ASIC shipments based on CoWoS wafer allocation and chips per wafer.

  The report further maps chip shipments to HBM demand, advanced process wafer consumption, and related revenue opportunities to identify supply chain bottlenecks and beneficiary segments.

• Scenario AnalysisPower Constraint Scenario Estimation

  Use an assumption of approximately 2kW average power consumption per GPU or ASIC to convert chip scale into data center power capacity demand.

  This estimate shows that about 19 million chips in 2027 may correspond to approximately 38GW of power demand, indicating that power infrastructure may limit the conversion of wafer and packaging capacity into actual deployment.

• Shipment AnalysisChip and Equivalent Rack Conversion

  Include HGX servers in the rack consumption model and assume that nine 8-GPU HGX servers are roughly equivalent to one NVL72 rack.

  This adjustment makes the matching between Blackwell chip output and end demand more complete, and also helps distinguish supply chain buffer inventory from true excess inventory.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• NVIDIA Corp.

  Core platform supplier for Rubin, Rubin Ultra, Blackwell, and supernode architectures.

  Strengths

  Has comprehensive platform capabilities spanning GPUs, NVLink, rack-level systems, and CPO interconnects, with Rubin series shipment scale expected to continue expanding.

  Weaknesses

  HBM shortages, cost pressure, and PCB and cooling issues in Kyber racks may force adjustments to product specifications and delivery plans.

  Comparison

  Compared with Chinese supernodes that more often use NPO solutions, NVIDIA tends to use CPO to strengthen cross-rack scaling performance.

  Risks

  Lower HBM specifications affecting long-context decoding performance, rack delays, insufficient power, and changes in customer capital expenditure.

• TSMC

  Key supplier of advanced processes and CoWoS packaging for AI GPUs and ASICs.

  Strengths

  CoWoS demand is growing rapidly, AI-related wafer and packaging revenue has high visibility, and AI-related revenue CAGR from 2024 to 2029 may reach about 60%.

  Weaknesses

  Capacity expansion for advanced packaging and advanced processes needs to be coordinated with equipment, materials, power, and customer project schedules.

  Comparison

  Its CoWoS capacity is the core link connecting GPU, ASIC, HBM demand, and final chip shipment estimates.

  Risks

  Insufficient end data center power, customer project delays, changes in capacity allocation, and geopolitical restrictions.

• MediaTek

  Important design partner for Google TPU projects and participant in subsequent 2nm products.

  Strengths

  ASIC market share is expected to reach 15% to 20% in 2027, with revenue share likely to rise further as 2nm TPU ramps in 2028.

  Weaknesses

  Revenue concentration and project execution depend on the mass production schedule of Google TPU, while design and validation complexity is high for advanced process products.

  Comparison

  Compared with Broadcom's existing TPU projects, MediaTek's participation in v8t and subsequent 2nm products is increasing.

  Risks

  Project delays, customer order adjustments, yield issues, and extended testing cycles.

• King Yuan Electronics Co Ltd

  Beneficiary of final testing, burn-in, and part of wafer probing for Google TPU and CPU.

  Strengths

  Longer AI chip testing times and higher reliability requirements help increase testing value per chip.

  Weaknesses

  Revenue contribution depends on customers' products ramping on schedule, and part of AI revenue has been delayed to the fourth quarter of 2026 and 2027.

  Comparison

  Compared with traditional chip testing, AI ASICs require longer testing cycles, burn-in, and system-level testing.

  Risks

  Customer project delays, fluctuations in testing equipment utilization, and rising customer concentration.

• SK hynix, Micron, Samsung Electronics

  Major potential suppliers of HBM3e, HBM4, and HBM4e.

  Strengths

  AI chips are driving significant growth in total HBM demand, and tight supply helps strengthen the strategic value of high-end memory.

  Weaknesses

  Tiered Rubin Ultra configurations may reduce the per-chip HBM capacity of some models and change the demand structure across different generations and stack specifications.

  Comparison

  Suppliers differ in HBM generation, stack height, certification progress, and shares in customer projects.

  Risks

  Customer specification reductions, capacity expansion faster than demand, certification delays, and yields falling short of expectations.

• CPO, NPO, high-speed PCB, and cooling supply chain

  Infrastructure segments supporting NVL576-class supernodes, cross-rack interconnects, and higher GPU density.

  Strengths

  Supernode scale expansion and higher compute density per rack bring higher value content for interconnects, PCBs, and cooling.

  Weaknesses

  Technical complexity is high, and the Kyber solution has already shown that PCB and thermal design may become mass production bottlenecks.

  Comparison

  NVIDIA leans toward CPO, while Chinese GPU vendors more often adopt NPO due to SerDes and process constraints.

  Risks

  Changes in technology roadmap, mass production yield, customer validation cycles, and rack deployment delays.

Key data

• Google TPU shipments3.7 million units in 2026; more than 7 million units in 2027, with the table estimating about 7.35 million unitsGrowth mainly comes from v8i, v8t, and subsequent 2nm products.
• Google CPU shipments1.5 million units in 2026; 3 million units in 2027Related projects require burn-in and system-level testing.
• TPU business contribution for King Yuan Electronics Co LtdApproximately 7% to 8% of revenue in 2026; slightly above 10% in 2027Includes final testing and part of wafer probing revenue.
• Google-related revenue for King Yuan Electronics Co LtdApproximately 8% to 10% of revenue in 2026; approximately 10% to 15% in 2027Covers TPU, CPU, final testing, and part of wafer probing.
• 2027 AI chips and power demandApproximately 19 million chips, corresponding to about 38GW of power capacityEstimated based on an average of about 2kW per GPU or ASIC.
• SpaceX expansion scenarioAn additional 8GW is approximately equivalent to more than 4 million Rubin GPUsRoughly equivalent to 20% of the number of AI accelerators TSMC can produce in 2027.
• Global CoWoS demand YoY growth102% in 2026; 93% in 2027Growth is jointly driven by NVIDIA, Broadcom, AMD, and custom ASIC customers.
• AI-related HBM demandUp to about 30 billion Gb in 2026; up to about 50 billion Gb in 2027Tiered HBM configurations may change per-chip usage and supplier shares.
• AI wafer revenue opportunityAt least US$26 billion in 2026; at least US$59 billion in 2027Estimated based on the processes, chiplet counts, and wafer prices for GPUs, ASICs, and CPUs.
• Blackwell shipmentsApproximately 5.4 million units in 2026Chip supply is expected to meet Grace Blackwell NVL72 demand in the second half of 2026.
• Rubin series shipmentsClose to 7 million units in 2027Rubin is expected to begin ramping in the third quarter of 2026, with rack shipments starting in the fourth quarter.
• Rubin NVL72 rack shipmentsApproximately 90,000 sets in 2027The actual pace depends on rack design, cooling, PCB, and interconnect solutions.
• TSMC AI-related revenue growthExpected compound growth rate of about 60% from 2024 to 2029Driven jointly by general-purpose AI chips, custom ASICs, CoWoS, wafer testing, and server CPUs.
• MediaTek's ASIC market share target15% to 20% in 2027The company believes its revenue share still has room to rise as 2nm TPU products ramp in 2028.

Impact & implications

Tiered HBM configurations may reduce the memory content of each high-end accelerator, easing short-term supply and cost pressure, but they will also reallocate demand across HBM generations, stack heights, and supplier shares. If lower per-chip memory leads customers to increase the number of chips, suppliers of GPUs, CoWoS, wafers, testing, and server components may gain additional volume growth. CPO and NPO will become important technical paths for expanding supernode scale, driving demand for optical modules, optical engines, advanced packaging, and high-speed PCBs. On the other hand, if power, cooling, and rack delivery cannot expand in sync, chip demand estimated at the wafer level may not translate into revenue on schedule.

Risks

• HBM capacity shortages or supplier certification delays may limit mass production of Rubin Ultra and other AI accelerators.
• Lowering HBM specifications may significantly affect decoding performance for long-context large models and weaken the competitiveness of some products.
• PCB, cooling, and system integration issues in Kyber racks may lead to delays in server and rack shipments.
• Global power infrastructure may be unable to support the AI chip deployment scale implied by wafer capacity.
• CoWoS advanced packaging, advanced process wafers, and testing equipment may see periodic supply-demand mismatches.
• If Google TPU, CPU, and other ASIC projects are delayed, it will affect revenue realization for MediaTek, GUC, and King Yuan Electronics Co Ltd.
• Export controls, U.S. executive orders, and related transaction restrictions may affect some companies, securities, and supply chain activities.
• Morgan Stanley has investment banking or other business relationships with multiple covered companies, and investors should pay attention to potential conflicts of interest.

What to watch

• NVIDIA's final decision on Rubin Ultra HBM specifications and product tiering before the end of the third quarter of 2026.
• The actual impact of HBM specification changes on long-context decoding performance, chip quantity demand, and HBM supplier shares.
• The mass production timetable for Kyber, Oberon NVL72, and NVL576 solutions, and whether PCB and cooling issues are alleviated.
• Customer adoption progress and mass production yields for CPO and NPO in cross-rack interconnects.
• Rubin's volume ramp in the third quarter of 2026 and the start of rack shipments in the fourth quarter.
• Whether demand for more than 7 million Google TPUs and 3 million CPUs in 2027 can be realized.
• MediaTek's revenue share in TPU projects and the ramp progress of 2nm products in 2028.
• Whether CoWoS capacity allocation, HBM supply, and data center power construction can remain synchronized.
• Whether Blackwell supply chain buffer inventory can be fully digested as expected within 2026.
• Validation of end demand through changes in cloud customer capital expenditure, AI chip leasing prices, and power capacity.