China's AI infrastructure is shifting from a single-chip race to system-level deployment and the token economy
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China's AI infrastructure is shifting from a single-chip race to system-level deployment and the token economy
J.P. Morgan believes WAIC 2026 shows that the competitive focus of China's domestic AI chip industry has shifted to Hopper-class effective computing power, PD-separated inference architecture, supernode deployment, and low-cost, broadly accessible token supply.
- The single-chip performance baseline has risen to effective Hopper-class, and domestic AI chip vendors need to deliver stronger effective computing power by late 2026 to 2027.
- The Prefill/Decode separation architecture has moved from experimentation to standardization, becoming an important mechanism for reducing the cost of large-scale LLM inference.
- Supernodes have become a key system-level solution to address the limits of domestic process nodes and the deployment needs of trillion-parameter large models.
- Agentic AI could significantly amplify token consumption, driving China to industrialize AI computing power in the form of a "token factory."
- The report favors Iluvatar CoreX, JCET, NAURA, and AMEC in the domestic AI supply chain.
Report interpretation
Overview
Based on J.P. Morgan's two-day visit to WAIC 2026, this report discusses changes in China's AI chip and AI infrastructure ecosystem. The report's core judgment is that China's AI infrastructure has shifted from benchmarking single-chip performance to system-level deployment, and from pure capacity expansion to an industrialization stage aimed at low-cost, highly accessible token supply.
Core views
First, the performance baseline for domestic AI chips is being reset to effective Hopper-class, with inference becoming a relatively clear commercialization use case for domestic GPUs, while training is seen as the next scalable market. Second, PD-separated inference architecture has become the standardized direction for reducing the cost of large-scale LLM inference. Third, supernodes alleviate the constraints of single-card performance and process nodes for domestic chips through system design involving chip interconnects, switching networks, software coordination, liquid cooling, and optical interconnects. Fourth, Agentic AI will drive infrastructure demand through token consumption several orders of magnitude higher than that of human users, pushing the "token factory" concept into practice.
Analysis framework
Based on on-site observations at WAIC 2026, the report combines changes in technical architecture, application-layer demand, supply-chain links, and stock implications, with a focus on evaluating investment opportunities in domestic AI chips, supernodes, advanced packaging and testing, and wafer fab equipment.
Methodology notes
Identify changes in China's AI infrastructure technology roadmap and the supply-chain segments that will benefit through conference visits.
The report translates on-site displays of chips, supernodes, and application trends into industry judgments and stock preferences.
Separate the prefilling and decoding stages in LLM inference to improve resource utilization efficiency and reduce inference costs.
The report believes this architecture has moved from the experimental stage into standardized application and is an important support for the commercialization of domestic GPU inference.
Form a unified computing domain through solutions such as multi-card interconnects, switching networks, software stacks, and thermal management.
The report believes supernodes are China's key answer to process constraints and the deployment needs of trillion-parameter models in AI infrastructure.
Asset mapping & comparison
Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).
- Iluvatar CoreX-H (9903.HK)Preferred target in the domestic AI chip supply chain
- Strengths
- The report believes it is well positioned among second-tier AI chip makers, with supply assurance and design wins at leading CSP customers, and it has launched the Tiangai 300 chip.
- Weaknesses
- It is still in the ramp-up stage of the domestic AI ecosystem and needs to prove sustained supply capability, software ecosystem strength, and large-scale deployment ability.
- Comparison
- The report sets effective Hopper-class computing power as the next-stage baseline and mentions that Tiangai 300 claims to outperform Hopper architecture by 10%-20% on some inference metrics.
- Risks
- Insufficient absolute performance of domestic chips at the single-card level, immature ecosystem, and uncertainty around customer deployment pace and supernode scale selection.
- JCET-A (600584.SS)Beneficiary target in advanced packaging and testing
- Strengths
- The report expects demand for advanced packaging and testing to increase alongside improvements in AI chips and system-level deployment.
- Weaknesses
- Affected by the semiconductor cycle, customer orders, and utilization of advanced packaging capacity.
- Comparison
- Compared with pure chip design companies, JCET is more of a beneficiary on the back-end service side of the AI supply chain.
- Risks
- AI chip volume growth below expectations, packaging and testing price competition, and fluctuations in the capex cycle.
- NAURA-A (002371.SZ)Preferred target in wafer fab equipment
- Strengths
- The report is positive on the WFE sector and believes memory and advanced logic wafer fab capex is strong.
- Weaknesses
- Equipment demand is highly correlated with the capex pace of wafer fabs.
- Comparison
- Like AMEC, it belongs to the report's preferred WFE direction and benefits from domestic semiconductor capacity expansion and demand for advanced logic.
- Risks
- Slower wafer fab investment, technology iteration falling short of expectations, and supply-chain and policy uncertainties.
- AMEC-A (688012.SS)Preferred target in wafer fab equipment
- Strengths
- The report believes it will benefit from memory and advanced logic wafer fab capex.
- Weaknesses
- Equipment orders and revenue recognition may be affected by customers' capacity expansion pace.
- Comparison
- Like NAURA, it is one of the report's preferred WFE names.
- Risks
- Volatility in semiconductor capex, changes in the pace of domestic substitution, and intensifying competition.
Key data
- Conference observation periodTwo-day WAIC 2026 visitThe report's views are based on J.P. Morgan's on-site observations at WAIC 2026.
- Performance baselineEffective Hopper-classThe report believes the key next-stage requirement for domestic AI chips is to reach effective Hopper-class computing power by late 2026 to 2027.
- Iluvatar CoreX Tiangai 300Selective inference metrics are 10%-20% higher than Hopper architectureThis figure was claimed by the company at the conference, and the report uses it as an example of domestic chip performance progress.
- Kimi K3 model scale2.8 trillion-parameter architectureThe report uses this to illustrate the need for supernode deployment for trillion-parameter LLMs.
- Supernode scaleFrom dozens of cards to thousands of cardsThe optimal scale still depends on different vertical scenarios and the maturity of ecosystem coordination.
- Covered companies and ratingsIluvatar CoreX-H 9903.HK, JCET-A 600584.SS, NAURA-A 002371.SZ, and AMEC-A 688012.SS are all rated OWThe report lists these companies as preferred names in the domestic AI supply chain.
Impact & implications
If the report's judgment holds, the focus of China's AI infrastructure investment will expand from single-point chip performance to system-level cluster capability, inference cost optimization, token supply industrialization, and domestic supply-chain coordination. Beneficiary areas include domestic AI chips, advanced packaging and testing, wafer fab equipment, liquid cooling, optical interconnects, and large-scale cluster software ecosystems.
Risks
- The absolute performance and ecosystem maturity of domestic AI chips still lag global leading solutions.
- Supernodes require continued coordination across chip interconnects, switching networks, software, liquid cooling, and optical interconnects, and ecosystem maturity is still insufficient.
- Industry standards for heterogeneous scheduling, token quality measurement, and the optimal supernode scale across different scenarios have yet to be clarified.
- If AI inference and training demand falls below expectations, it could affect volume growth for domestic GPUs, packaging and testing, and equipment supply chains.
- Valuations of related stocks may be affected by the semiconductor capex cycle, customer onboarding pace, and the policy environment.
What to watch
- Whether domestic AI chips can achieve effective Hopper-class computing power by late 2026 to 2027.
- Deployment progress of PD-separated inference architecture among leading customers and in real business scenarios.
- Commercialization of supernodes from dozens to thousands of cards, as well as the maturity of interconnect solutions and software stacks.
- The actual boost from Agentic AI applications to token consumption and computing power demand.
- Whether memory and advanced logic wafer fab capex continues to support WFE demand.
- Subsequent orders, capacity, customer onboarding, and rating target price changes for Iluvatar CoreX, JCET, NAURA, and AMEC.