UBS: Strong Asia Semiconductor AI Outlook in 2026; Reiterates Buy on TSMC

Overview

This report provides an in-depth analysis of the robust outlook for Asia’s semiconductor industry in 2026, driven by cloud AI. Its central thesis is that surging demand for GPUs and ASICs will further cement TSMC’s leadership in advanced nodes (N3/N2) and advanced packaging (CoWoS). Concurrently, evolving dynamics in the Google TPU ecosystem present a structural growth opportunity for MediaTek. The report quantifies the revenue and capacity impact of each 1GW of AI server deployment on TSMC and analyzes how co-packaged optics (CPO) will reshape the supply chain. Overall, the report maintains or initiates Buy ratings on TSMC, MediaTek, ASE Group, ASPEED Technology, and others, positioning the sector at the early stage of a profitability upgrade cycle.

Core views

Key View 1: TSMC’s leadership remains solid, with robust demand for advanced nodes. The report forecasts TSMC’s N2 node demand to reach ~220k wpm by 2028—exceeding N3’s third-year production volume. Despite competition from Samsung and Intel, TSMC retains over 80% market dominance in advanced packaging and technological leadership. Furthermore, Agentic AI is driving explosive growth in server CPU demand, with global server CPU shipments projected to rise from 23M units in 2025 to 63–70M units by 2030. Rising ARM architecture and AMD market shares are expected to significantly benefit TSMC. Key View 2: MediaTek faces a structural opportunity in the Google TPU market. As Google internalizes some front-end TPU design and adopts a dual-track strategy, MediaTek—leveraging its cost advantage (TPU design service fees >50% lower than Broadcom’s)—is gaining share. The report projects MediaTek’s share in Google’s TPU market rising from 11% in 2026 to 34% in 2027, corresponding to TPU revenues of $16B in 2027 and $30.5B in 2028. This transition positions MediaTek as a true cloud-and-edge AI fabless design house and delivers substantial operating leverage. Key View 3: Quantifying AI server build-out impact on TSMC. Each 1GW of AI server deployment requires ~20–50k wpm of advanced-node (N3/N2) wafer capacity and ~30–60k wpm of CoWoS capacity, generating $1–2B in incremental revenue for TSMC—representing ~1.0–1.5% of its total sales. With new platforms such as NVIDIA Rubin Ultra and Feynman entering the market, TSMC’s value content per rack is expected to increase beyond Blackwell’s ~5%. Key View 4: Advanced packaging and CPO reshaping the supply chain. CoWoS capacity is projected to expand to 210k wpm by end-2027 but will remain constrained. Though still in its infancy, CPO technology is expected to mature within the next three years and achieve broad adoption in GPU scaling by 2029. CPO development will strengthen TSMC’s moat in cloud AI and open new market opportunities for vendors like ASE Group, which possess capabilities in fiber array unit coupling and switchboard packaging.

Analysis framework

The report employs a hybrid top-down and bottom-up analytical framework. First, it examines multi-gigawatt (GW)-scale AI data center deployments from a macro perspective to quantify upstream semiconductor capacity requirements—particularly for TSMC’s advanced nodes and CoWoS—driven by AI acceleration and server CPUs. Second, it dissects evolving dynamics in the Google TPU ecosystem, comparing Broadcom’s and MediaTek’s cost structures and service models to derive MediaTek’s share gain logic. Third, for frontier technologies such as CPO, the report maps out technology maturity timelines and assesses impacts across the value chain—including optical engines, packaging, and testing—to identify potential beneficiaries. Finally, company-specific financial guidance, capital expenditure plans, and valuation metrics are integrated to formulate stock ratings and target prices.

Methodology notes

• Industry/sector analysis frameworkSupply-demand framework

  Assesses industry bottlenecks and pricing trends by analyzing the expansion of supply (e.g., advanced-node (N3/N2) and CoWoS capacity) against demand growth (e.g., AI accelerators, server CPUs).

  The report concludes that advanced-node and packaging capacity will remain constrained by comparing supply expansion plans (e.g., TSMC’s N2 capacity reaching 140k wpm by 2027) with downstream demand (e.g., wafer consumption per 1GW of server deployment). This forms the core logic underpinning TSMC’s pricing power and premium valuation.

• Industry/sector analysis frameworkVolume-price decomposition

  Breaks down each 1GW of AI server deployment into discrete chip counts, wafer capacity requirements, and packaging needs, then calculates TSMC’s associated revenue contribution.

  Rather than making generic statements about AI’s benefits to TSMC, the report precisely calculates incremental revenue—$1–2B per 1GW—by multiplying ‘volume’ (xPU/CPU count per GW) by ‘price’ (foundry and packaging fees per chip), delivering a rigorous, quantified investment thesis.

• Competition and strategy frameworkMoat / competitive advantage

  Analyzes TSMC’s technological barriers and customer stickiness in advanced nodes and advanced packaging (CoWoS/SoIC).

  The report highlights that TSMC’s moat stems not only from leading-edge process technology but also from vertically integrated supply chain resilience (e.g., localized supply chains in Taiwan) and one-stop advanced packaging services—making it difficult for competitors to erode its >80% market share in the near term.

• Valuation methodologyPE/PEG valuation

  Uses price-to-earnings (PE) ratios and expected earnings growth rates to assess stock valuation reasonableness.

  In deriving target prices, the report widely applies PE multiples—for example, assigning TSMC a 2027E PE of 17x and MediaTek 2027–28E PE of 26x—while justifying valuations using long-term compound annual growth rate (CAGR) projections. This relative valuation method is standard practice in the semiconductor industry.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• TSMC (2330.TW)

  Beneficiary: As the primary foundry and packaging partner for AI chips from NVIDIA, AMD, and Google, directly benefits from tight advanced-node and CoWoS capacity.

  Strengths

  Technology leadership, rapid N2/N3 capacity ramp, integrated advanced packaging capability, >80% market share.

  Weaknesses

  Geopolitical risk, depreciation pressure from overseas capacity expansion.

  Comparison

  Higher execution capability and customer trust versus Samsung and Intel.

  Risks

  Demand shortfall, intensified competition triggering price wars.

• MediaTek (2454.TW)

  Beneficiary: Gaining market share in Google TPU design services, displacing Broadcom.

  Strengths

  Significant cost advantage, SerDes technology expertise, stable smartphone business base.

  Weaknesses

  Short-term increased reliance on a single customer (Google), execution risk.

  Comparison

  Lower service fees than Broadcom, offering better value-for-money.

  Risks

  Faster-than-expected internalization of TPU design by Google, technology iteration failure.

• ASE Group (3711.TW)

  Beneficiary: Surging demand for advanced packaging (LEAP/CoWoS-related) and testing services.

  Strengths

  World’s largest OSAT, comprehensive technology portfolio, close collaboration with TSMC.

  Weaknesses

  Massive capex burden, margin pressure from depreciation.

  Comparison

  Market-leading share in high-end packaging versus peers.

  Risks

  Fluctuating utilization rates, slower-than-expected technology upgrades.

• ASPEED Technology (5274.TWO)

  Beneficiary: Growing demand for server BMC chips aligned with AI server shipment growth.

  Strengths

  Market leadership, ramp-up of new AST2700 product.

  Weaknesses

  Product lifecycle volatility.

  Comparison

  No peer competitor of comparable scale in the BMC space.

  Risks

  Slower server shipment growth, pricing pressure.

Key data

• TSMC N2 Demand Forecast~220k wpm (2028E)Expected to exceed N3’s third-year production demand level
• MediaTek TPU Revenue ForecastUS$16bn (2027E) / US$30.5bn (2028E)Driven by Google TPU market share rising from 11% to 34%
• Revenue Impact on TSMC per 1GW AI Server DeploymentUS$1–2bnRepresents ~1.0–1.5% of TSMC’s total sales
• CoWoS Capacity Forecast210k wpm (end-2027E)Including 150k wpm from TSMC and 60k wpm from OSATs; capacity remains tight
• ASE Group CapexUS$8.5bn (2026E)Up from $5.5bn in 2025, reflecting strong demand for advanced packaging
• Global Server CPU Shipment Forecast63–70m units (2030E)CAGR of ~30% from 2025–2030; rising ARM and AMD shares

Impact & implications

The report argues that the AI wave is expanding beyond GPU-based training into broader inference, edge computing, and customized ASIC applications—diversifying value distribution across the semiconductor supply chain. As the central foundry and packaging platform, TSMC will continue capturing the largest share of value-added growth. MediaTek’s success illustrates how fabless design companies can achieve re-rating by securing positions in cloud ASIC markets. For OSATs and materials suppliers, the introduction of CPO and increasingly complex packaging technologies raises both technical barriers and value content—benefiting leaders such as ASE Group and Giga Semiconductor via rising industry concentration and ASP uplift from technology upgrades.

Risks

• AI demand falling short of expectations, leading to capacity oversupply
• Escalating geopolitical tensions disrupting supply chain stability
• Technology iteration risks, e.g., slow yield ramp for CPO or new process nodes
• Macroeconomic downturn affecting consumer electronics and traditional server demand
• Intensified competition—especially from Chinese players in mature-node foundry—pressuring pricing

What to watch

• TSMC’s N2 and N3 utilization rates and pricing power
• Production ramp timeline for Google TPU v8t/v9 and MediaTek’s share evolution
• CPO penetration rate in NVIDIA Rubin/Feynman platforms
• Pricing negotiation outcomes and utilization recovery in mature-node foundries
• Implementation progress of U.S. CHIPS Act subsidies and domestic capacity buildout