Beyond Moore’s Law: Chip Stacking Technology Sees Sevenfold Growth

Overview

Bernstein has released an extensive industry report noting that, as Moore’s Law loses its economic viability at nodes below 10nm and the “memory wall” emerges as a performance bottleneck, advanced packaging—particularly chip‑to‑wafer stacking technology—is becoming a critical pathway for boosting semiconductor performance. The report forecasts that by 2030, monthly wafer capacity leveraging stacking technologies will surge from roughly 500,000 wafers in 2025 to 3.5 million, representing a sevenfold increase, with penetration rising from 7.4% to 37%. This trend is not confined to the AI sector; it will also extend broadly to DRAM, NAND, and advanced logic chips. In light of this long-term trajectory, the firm remains bullish on backend equipment suppliers, maintaining an “Outperform” rating for DISCO, Tokyo Electron, and Besi, while assigning a “Market Perform” rating to Sumco.

Core views

The economic benefits of Moore’s Law have peaked around the 10nm node, making it increasingly difficult to sustain cost reductions and performance gains solely through further transistor scaling. Meanwhile, surging demand for computing power from AI and high-performance computing has turned interconnect speed—often referred to as the “memory wall”—into a new bottleneck. Stacking technologies, which integrate multiple chips vertically or horizontally via 2.5D or 3D approaches, significantly boost interconnect speeds, enabling multi-chip designs to operate with the same efficiency as single‑chip solutions. For example, Nvidia’s Hopper and Blackwell GPU families extensively leverage HBM stacking technology. In terms of market scale, the adoption of stacking technologies is accelerating rapidly. In 2025, only about 500,000 wafers per month will incorporate stacking, accounting for 7.4% of total wafer consumption. Bernstein forecasts that by 2030, this figure will climb to 3.5 million wafers per month, representing 37% of total shipments. Among these, high-bandwidth memory (HBM), NAND CMOS bond‑array (CBA) hybrid bonding, and DRAM CBA are expected to be the primary contributors to production volume. Although logic‑chip stacking—such as CoWoS, 3D ICs, and BSPDN—remains relatively small in absolute terms, its high value-added nature ensures it will play a pivotal role in terms of revenue. On the technology front, HBM, currently the largest stacking application, is projected to see TSV capacity double from 390,000 wafers per month at the end of 2025 to 700,000 wafers per month by 2027, driven primarily by demand from Nvidia GPUs and ASICs. CoWoS, the de facto standard packaging solution for AI GPUs, is expected to reach a capacity of 142,000 wafers per month by 2027. Additionally, wafer‑level multi‑chip modules (WMCM) are poised to replace InFO as the dominant packaging technology for mobile devices such as iPhones by 2027, with capacity projected to surpass that of CoWoS. In the storage sector, NAND CBA technology separates CMOS circuitry from storage cells during fabrication and then bonds them together, dramatically increasing density and read/write speeds while reducing power consumption. DRAM CBA is also expected to ramp up significantly after 2028, employing wafer‑to‑wafer bonding to overlap core and peripheral circuits, thereby saving chip area and improving yield. From an investment perspective, backend equipment suppliers are positioned as long-term beneficiaries. DISCO, a leading provider of grinding and dicing equipment, stands to gain from capacity expansions in existing applications as well as from the heightened cleanliness and thickness‑control requirements of emerging technologies like hybrid bonding. Besi, a pioneer in hybrid bonding with a 91% market share, has further strengthened its competitive moat through collaboration with Applied Materials. Tokyo Electron, a leader in wafer‑to‑wafer bonding equipment, will directly benefit from the adoption of 3D NAND CBA and BSPDN. Meanwhile, Sumco, a major silicon wafer supplier, faces risks from Chinese competition and renegotiations of long-term contracts; however, the growing demand for advanced‑node silicon wafers driven by stacking technologies provides a tactical rationale for bullish positioning.

Analysis framework

The research report first establishes two key industry backdrops—the “economic obsolescence of Moore’s Law” and the “memory wall bottleneck”—before introducing “3D stacking technology” as the central rationale for addressing these challenges. Subsequently, the firm employs a quantitative forecasting model to project the growth trajectories of wafer capacity for various stacking technologies—including HBM, CoWoS, CBA, and BSPDN—between 2025 and 2030, thereby substantiating the long-term nature of this trend and its scale‑economy effects. Finally, drawing on supply‑chain transmission dynamics, the report identifies equipment manufacturers (DISCO, Besi, TEL) and upstream materials suppliers (Sumco) that hold monopolistic positions or technological advantages in the backend packaging segment, and, taking into account their respective competitive landscapes and risk factors, assigns specific ratings and target prices.

Methodology notes

• Industry/ Sector Analysis FrameworkSupply-and-Demand Framework

  Post-Moore’s Law Technological Substitution Paths

  As the diminishing marginal cost reductions from conventional process scaling reach their limits, the industry is turning to alternative packaging architectures—such as 3D stacking—to meet performance demands. This reflects a quintessential supply-side technological innovation aimed at addressing the insatiable demand for computing power on the demand side.

• Industry/ Sector Analysis FrameworkUpstream–Midstream–Downstream Transmission in the Industrial Chain

  Technological advancements in packaging are driving demand for upstream equipment and materials.

  The research report analyzes the transmission chain—from demand for edge AI chips to the expansion of advanced packaging (stacking) capacity and the resulting growth in demand for back-end specialized equipment (bonding, dicing) and raw materials (silicon wafers)—and uses this framework to identify beneficiary stocks.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• DISCO (6146.JP)

  Benefit: Provides the grinding and cutting equipment required for stacking.

  Strengths

  The company has established a strong foothold in the advanced packaging sector, and emerging applications that demand higher precision are driving added value.

  Risks

  AI-related overcapacity leading to valuation compression; changes in the competitive landscape; exchange rate volatility.

• Tokyo Electron (8035.JP)

  Benefit: A leader in wafer-to-wafer bonding equipment

  Strengths

  It holds a dominant position in the 3D NAND CBA and BSPDN segments, while also developing die-to-wafer equipment.

  Risks

  U.S. trade restrictions are impacting capital expenditures in China and globally; semiconductor demand is slowing; and exchange-rate volatility persists.

• Besi (BESI.NA)

  Benefit: A pioneer in hybrid bonding technology with a 91% market share.

  Strengths

  Collaborating with AMAT to integrate front-end processes, creating a deep competitive moat.

  Risks

  Mixed bonding adoption falls short of expectations or is delayed; the mainstream assembly market recovers slowly; and market share is eroding.

• Sumco (3436.JP)

  Benefit: Stacking technology increases the consumption of advanced-node wafers.

  Strengths

  Major silicon wafer suppliers are directly benefiting from rising demand.

  Weaknesses

  Facing pressure from Chinese competitors; risks associated with the renegotiation of long-term agreements

  Risks

  Global economic weakness is weighing on electronics demand; inventory destocking is proceeding more slowly than expected; exchange rate volatility.

Key data

• 2025 Wafer Stacking CapacityApproximately 500,000 units per monthAccounting for 7.4% of total wafer consumption
• 2030 Wafer Stacking Capacity Forecast3.5 million units per monthFive-year growth of sevenfold, with a penetration rate reaching 37%
• HBM TSV Capacity Forecast (2027E)700,000 units per monthNearly double the 390,000 wafers per month as of end-2025.
• CoWoS Capacity Forecast (2027E)142,000 units/monthTSMC is the primary supplier, and its production capacity is already fully utilized.
• NAND CBA Capacity Forecast (2030E)1.057 million units per monthOne of the key contributors, increasing density by 50%
• BSPDN Capacity Forecast (2030E)285,000 units/monthBackplane power delivery network technology boosts performance by 8–10%.

Impact & implications

For the semiconductor industry, stacking technology has evolved from an AI‑specific “luxury” to a “must‑have” for most advanced chips over the next five years. This shift implies that the share of packaging in the overall cost structure of semiconductors will rise significantly, with the industry’s focus gradually shifting from front‑end manufacturing to back‑end packaging. For investors, the emphasis should broaden beyond mere process‑node advancements to encompass the packaging technology roadmap and its associated equipment supply chain. Equipment suppliers such as DISCO, Besi, and Tokyo Electron, owing to their monopolistic positions or leading market roles in this space, enjoy substantial pricing power and greater earnings visibility.

Risks

• Overcapacity in AI-related production (such as GPUs and HBM) has resulted in a double whammy, weighing on both valuation multiples and profitability.
• The competitive environment has undergone adverse changes.
• Exchange rate fluctuations have had a negative impact on revenue.
• Changes in U.S. trade restriction policies are unfavorable to both China’s and the global semiconductor capital expenditure.
• Global semiconductor demand (for both logic and memory) has slowed, prompting cuts in capital expenditures.
• Adoption of hybrid bonding technology falls short of expectations or is delayed.
• Chinese competitors are catching up faster than expected.

What to watch

• HBM and CoWoS capacity expansion progress and utilization rates
• The mass-production timelines and market penetration rates of NAND and DRAM CBA technologies.
• The implementation status of BSPDN technology at Intel’s 18A and TSMC’s A16 process nodes
• Order visibility among major equipment vendors and changes in the market share of hybrid bonding.