J.P. Morgan Initiates Coverage on V-Test: Leader in AI Chip Testing, Target Price RMB 220

Overview

J.P. Morgan initiates coverage on V-Test (688372.SH) with an Overweight rating, setting a target price of RMB 220 for June 2027. The core logic of the report is that under external constraints forcing domestic AI chips to accelerate the adoption of the Chiplet (multi-die) architecture, the independent third-party testing segment is experiencing structural incremental growth. Leveraging the largest reserve of high-end tester tools in A-shares and a counter-cyclical capacity expansion strategy, V-Test is poised to double its market share and significantly repair profitability over the next three years.

Core views

The Chipletization of domestic AI chips brings a structural explosion in testing demand. The report points out that constrained access to advanced process equipment forces domestic AI chips to accelerate their shift toward the Chiplet architecture, which directly amplifies testing demand. Specifically, multi-die design creates a 1.5-2x multiplier effect on the volume and complexity of wafer probing (CP), while final test (FT) time increases by 1.2-1.5x. Institutions calculate that China's AI chip testing demand will grow at a CAGR of 88% from 2026-2028, far exceeding the overall testing market's 23% growth rate. By 2028, AI testing will account for approximately 30% of total demand. Furthermore, the highly fragmented ecosystem of domestic AI chips further intensifies reliance on third-party professional testing services. Counter-cyclical expansion and equipment barriers establish first-mover advantage. V-Test is the firm with the highest installation volume among pure third-party testing companies in A-shares. As of the end of 2025, it possessed over 1,500 testers, including more than 400 high-end models. During the industry downturn, the company's capital expenditure reached RMB 2.9 billion in 2025 (accounting for 187% of revenue). This counter-cyclical investment allowed it to seize the initiative in customer validation and high-end equipment delivery. Although high depreciation has caused market concern, the company's capacity utilization remains above 80%. With the introduction of high-value-added AI orders, revenue growth (projected at 65%/50% for 2027/2028) will significantly outpace depreciation growth, and economies of scale are about to manifest. Product structure upgrade drives profitability repair. The report emphasizes that AI chip testing commands higher unit prices and gross margins than traditional consumer SoCs due to equipment scarcity and engineering complexity. As the revenue share of computing chips rises from 20% in 2025 to over 35% in 2028, and the high-margin CP business maintains a share of around 60%, the company's comprehensive gross margin is expected to gradually recover from a low of 37.1% in 2024 to 44.6% in 2028. Institutions predict the company's revenue and net profit CAGRs for 2026-2028 will reach 59% and 73% respectively, with market share potentially rising from approximately 10% to over 20%. Valuation is attractive with multiple catalysts. The current stock price corresponds to approximately 29x one-year forward P/E, representing a 40% discount to the average level of A-share OSAT peers (50x). The target price of RMB 220 is based on 30x one-year forward PE, referencing the company's three-year historical mean and applying a 30% discount to OSAT peers to reflect the risk of limited short-term pricing flexibility. Catalysts for future valuation repair include: revaluation driven by expanded AI business exposure, ASP upward support from product mix optimization, and superior profitability quality compared to OSAT peers.

Analysis framework

The report adopts a deduction chain of "technological path change → quantification of testing workload → supply-demand gap analysis → matching with individual company competitive advantages." It starts from the technological constraint of domestic AI chips being forced to adopt the Chiplet architecture, transforming technical changes into measurable increments in testing workload by setting specific multiplier coefficients (CP 1.5-2x, FT 1.2-1.5x). Secondly, combining the fragmentation of the domestic AI ecosystem and trends in third-party testing penetration, it derives industry-level supply-demand gaps. Finally, by comparing leading indicators such as the company's high-end equipment inventory, capital expenditure intensity, and customer coverage, it demonstrates the certainty of capturing these increments, utilizing DuPont analysis and peer valuation comparisons to anchor the pace of profitability repair and reasonable pricing ranges.

Methodology notes

• Industry/Industrial Analysis FrameworkVolume-Price Breakdown

  Multiplier Effect of Chiplet Architecture on Testing Workload

  Instead of vaguely stating that AI drives testing demand, the report breaks down Chiplet technical characteristics into specific testing workload multipliers (CP test volume x1.5-2x, FT time x1.2-1.5x). This method transforms abstract technological trends into quantifiable and verifiable business increment assumptions, serving as a key quantitative tool when analyzing the impact of technological changes on the industrial chain.

• Competition and Strategy FrameworkMoat / competitive advantage

  Counter-Cyclical Capital Expenditure Barriers in Asset-Heavy Industries

  In asset-heavy industries like semiconductor testing, equipment delivery cycles are long and customer verification thresholds are high. The report analyzes the company's high capital expenditure during the industry downturn (Capex/Revenue reaching 187%) to demonstrate its strategy of building capacity and equipment barriers using time lags. This first-mover advantage formed by counter-cyclical investment constitutes a competitive moat that latecomers find difficult to overcome in the short term.

• Valuation MethodPE/PEG valuation

  Relative Valuation Anchoring Based on Growth and Peer Discount

  When determining the target price, the report did not simply apply the industry average PE but selected the company's own historical mean as a benchmark, applying a 30% discount relative to OSAT peers to reflect the risk of weaker short-term pricing power. This valuation method balances the company's growth potential (high PEG potential) with current competitive position constraints, avoiding simple bullishness or rigid application of past metrics.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• V-Test (688372.SH)

  Core Beneficiary: Largest pure third-party testing vendor in A-shares, directly absorbing incremental testing demand brought by the Chipletization of domestic AI chips

  Strengths

  Leading industry reserve of high-end testers; counter-cyclical expansion locks in capacity; covers mainstream domestic AI chip design companies; high CP business share benefits gross margin structure

  Weaknesses

  High depreciation in the short term suppresses profit performance; relatively weaker pricing flexibility compared to OSAT manufacturers; dependence on procurement of overseas high-end equipment

  Comparison

  Compared to domestic peers like Liyang Semiconductor and Hualing Microelectronics, V-Test has advantages in high-end equipment scale and AI customer coverage; compared to OSATs like JCET, its neutral third-party positioning better fits the needs of Fabless manufacturers

  Risks

  Restrictions on testing equipment procurement may hinder expansion progress; export control policy changes may affect the return of testing orders from overseas fabs; advancement of domestic ATE equipment lowers industry barriers; non-AI demand recovery falls short of expectations

Key data

• 2026-28E Revenue/Net Profit CAGR59% / 73%Benefiting from the explosion in AI chip testing demand and product structure upgrade
• AI Chip Testing Demand Growth (2026-28E)88% CAGRFar exceeding the 23% growth of the overall testing market, accounting for 30% by 2028
• Chiplet Architecture Testing Increment CoefficientCP 1.5-2x / FT 1.2-1.5xMultiplication of test volume and time caused by multi-die design
• 2025 Capital ExpenditureRMB 2.9 BillionEquipment expenditure approx. RMB 2.5 billion, Capex/Revenue ratio reaching 187%
• Tester Scale (End of 2025)1500+ units (High-end >400 units)Largest scale among pure third-party testing companies in A-shares
• 2028E Comprehensive Gross Margin Forecast44.6%Significant recovery from the 2024 low of 37.1%; was 39.4% in 2025
• Target Price and Valuation MultipleRMB 220 / 30x 1Y Fwd PEApproximately 40% discount to the average OSAT peer PE of 50x

Impact & implications

The report believes that V-Test is positioned at a critical juncture in the explosion of the domestic AI supply chain. For investors, this means the company is no longer just a follower of traditional semiconductor cycles but possesses structural growth attributes as part of AI computing infrastructure. In the short term, depreciation pressure from high capital expenditures will be absorbed by highly certain AI orders. In the medium to long term, as the penetration rate of third-party testing systematically improves within the domestic chip industry chain, the company is expected to shift from simple capacity expansion to structural improvement in profit margins, and its valuation system may also be reshaped from traditional packaging and testing to an AI computing supporting service provider.

Risks

• Testing equipment procurement restrictions may hinder capacity expansion progress
• Changes in export control policies may affect the return of testing orders from overseas wafer fabs
• The rise of domestic ATE equipment providers leads to intensified industry competition and lowered barriers
• Recovery of non-AI chip demand (e.g., consumer electronics) is weaker than expected

What to watch

• Mass production progress of domestic AI chip Chiplet solutions and actual landing of testing orders
• Arrival schedule of high-end testing equipment and changes in capacity utilization
• Whether quarterly gross margin repair trends align with financial model expectations
• Tape-out and shipment dynamics of major domestic AI chip design companies