Dynamic area borrowing breaks through the effective active-region bottleneck of 2nm GAA, increasing module maximum frequency by up to 9.8%

Overview

This report is a technical presentation from the 2026 IEEE VLSI Symposium on Technology and Circuits, studying the effective active-region width bottleneck for 2nm gate-all-around standard cells amid continued cell-height scaling and saturation of contacted poly pitch. Samsung Electronics Co. Ltd's foundry business proposes a dynamic area borrowing architecture that uses backside power delivery and direct backside contacts to remove the rigid inter-row boundaries caused by frontside power delivery networks, allowing high-drive cells to use spatial margin in adjacent rows on demand.

Core views

Performance and area scaling at advanced nodes are diverging: reducing cell height helps density but compresses the effective active region and weakens drive capability; traditional mixed track-height schemes also create placement fragmentation and utilization losses. Dynamic area borrowing restores wide nanosheet cell options by extending PMOS or NMOS on one side and places the active region using a center-reference approach to reserve space for cross-row expansion. Both cell-library and module evaluations show performance improvements without area overhead, indicating that this method may extend the performance boundary of 2nm GAA logic design.

Analysis framework

The study first analyzes the scaling conflict among contacted poly pitch, cell height, and effective active-region width, then uses a variable-lane analogy to illustrate resource idleness caused by fixed row boundaries. It then adopts a design-technology co-optimization approach to build a dynamic area borrowing standard-cell library, validating the scheme through cell-level delay measurement, Cadence Innovus placement legalization, and Cortex-A72 ID module-level power performance area evaluation.

Methodology notes

• Design-technology co-optimizationDynamic area borrowing architecture

  Dynamically borrowing space across standard-cell rows

  Backside power delivery and direct backside contacts eliminate the constraints imposed by frontside power structures on row boundaries, enabling cells requiring higher drive capability to use unused spatial margin in adjacent rows.

• Standard-cell physical designCenter-reference active-region positioning and one-sided extension

  Increasing effective active-region width while ensuring placeability

  The active region is moved toward the cell center to create margin for cross-row expansion, and PMOS or NMOS is selectively extended to balance drive capability and placement legality.

• Electronic design automation validationDynamic area borrowing-aware implementation flow

  Edge grouping, constrained placement, and automatic legalization

  Specific types are defined for cell edges to prevent illegal abutment, and legalization is completed through Cadence Innovus constraints and automatic cell migration, validating design implementability.

• Power performance area evaluationHierarchical validation at cell and module levels

  Layer-by-layer validation from cell delay to module maximum frequency and area

  Average delays of different cell libraries are first compared against the N2 baseline, followed by evaluation of maximum frequency, core area, and the area share of various standard-cell types using the Cortex-A72 ID module.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• Samsung Electronics Co. Ltd foundry business

  Technology proposer and potential beneficiary of the 2nm GAA process platform

  Strengths

  It has co-development capabilities across backside power delivery, GAA devices, standard-cell libraries, and design flows, and the study demonstrates cell-level and module-level performance validation.

  Weaknesses

  The public materials do not provide yield, absolute power consumption, manufacturing cost, or customer production adoption status.

  Comparison

  Compared with traditional mixed track-height schemes, dynamic area borrowing reduces placement fragmentation caused by fixed tall cells and allocates adjacent-row space according to demand.

  Risks

  Production design rule complexity, EDA tool support, illegal abutment control, yield, and the stability of benefits under different design workloads still need validation.

• Advanced-process EDA and standard-cell ecosystem

  Implementation support link for the dynamic area borrowing architecture

  Strengths

  The Cadence Innovus flow has demonstrated capabilities in edge grouping, placement constraints, and automatic legalization.

  Weaknesses

  New design kits, cell-edge rules, and dynamic area borrowing-aware constraints are required, which may increase flow maintenance costs.

  Comparison

  This method does not rely solely on device scaling, but jointly optimizes process structures, cell architecture, and physical implementation.

  Risks

  There is uncertainty around cross-tool compatibility, signoff coverage, and convergence efficiency in large-scale complex chips.

Key data

• Average cell-level delay reductionN3P is 9%, N3N is 5%Versus the N2 baseline, the report summarizes the conclusion as a 5% to 9% delay reduction across the library.
• Module maximum frequency improvement9.8%The frequency ratio of the Cortex-A72 ID module increases from 1.000 to 1.098.
• Core area ratio0.929The baseline is 1.000, corresponding to an approximately 7.1% reduction in core area with no area overhead.
• Standard-cell area share of the proposed schemeN1 is 65.42%, N2 is 25.36%, N3 is 9.22%In the baseline, N1, N2, and N3 are 66.25%, 34.75%, and 0.00%, respectively; the higher N1 share provides spatial margin available for dynamic area borrowing.

Impact & implications

This result shows that logic performance improvement at the 2nm GAA node does not have to rely entirely on higher fixed cell tracks or larger layout area, but can be achieved through cross-row resource sharing supported by backside power delivery. If incorporated into production design platforms, this method is expected to enhance the competitiveness of high-performance logic libraries, improve the frequency-density combination at advanced nodes, and increase the system value of backside power delivery technology. Because the report is a technical validation rather than a commercial forecast, it cannot directly imply impacts on revenue, market share, or securities valuation.

Risks

• The results mainly come from a specific cell library and the Cortex-A72 ID test module, and do not prove that all chip architectures and workloads can obtain equivalent benefits.
• The report does not disclose absolute power consumption, changes in static and dynamic power, yield, thermal effects, or manufacturing cost.
• Dynamic area borrowing depends on backside power delivery and direct backside contacts, and the maturity of related processes may affect production timing and economics.
• Edge types, adjacency rules, and automatic legalization increase physical design complexity, and timing convergence and signoff in large-scale designs still need to be tested.
• The materials are from a technical conference presentation and do not include securities ratings, target prices, orders, or evidence of commercialization revenue.

What to watch

• The production schedule, yield, and customer adoption of 2nm GAA and backside power delivery platforms.
• Whether the dynamic area borrowing standard-cell library enters official process design kits and commercial design flows.
• Frequency, power, area, and routing congestion results in larger-scale modules and different logic architectures.
• The degree of native EDA tool support for cross-row space borrowing, legalization, timing signoff, and design rule checking.
• The stability of performance gains under different N1, N2, and N3 cell combinations and different spatial-margin conditions.