Samsung demonstrates three-layer nanosheet 3DSFET with 42 nm gate pitch for the first time

Overview

The report focuses on three-dimensional stacked field-effect transistors for advanced logic applications. In response to the standard-cell height scaling limitations that remain after the evolution from FinFET to GAA MBCFET, Samsung Electronics proposes and demonstrates a 3DSFET with a 42 nm gate pitch and three-layer nanosheet channels in both the upper and lower tiers. The work covers device structure, key process integration, and validation of electrical characteristics, aiming to prove the feasibility of this architecture in further reducing cell height while maintaining effective channel width.

Core views

The core conclusion is that 3DSFET can vertically stack n-FETs and p-FETs to drive cell height below 100 nm while maintaining sufficient effective channel width. This sample reduces the gate pitch from the previously demonstrated 48 nm to 42 nm, and increases the upper/lower channel stack from 2/2 layers to 3/3 layers. Multilayer epitaxy, interlayer dielectric isolation, vertical patterning of N/P gate work-function metals, and through-type common source/drain contacts all received structural or electrical validation, indicating preliminary feasibility for full-flow integration. However, incomplete top source/drain epitaxy causes leakage dispersion in n-FETs, variations in bottom inner-spacer gate length lead to p-FET threshold-voltage fluctuations, and the survival rate of common source/drain devices and circuit-level functionality still need improvement.

Analysis framework

The report adopts a methodology combining technology-generation comparison, step-by-step integration of key modules, and wafer-level electrical statistics. It first compares the VLSI 2024 and VLSI 2025 schemes with this work in terms of channel layer count, gate pitch, contact structure, and device functionality; then presents process flows for epitaxial growth, interlayer dielectric formation, vertical gate patterning, and through contacts; finally, it evaluates device functionality and uniformity using on/off ratio, survival rate, subthreshold swing, saturation current, off-state current, and linear threshold-voltage distribution.

Methodology notes

• Device architectureThree-dimensional stacked field-effect transistor scaling analysis

  Increase effective channel width per unit area through vertical stacking of upper and lower transistors, while further compressing standard-cell height.

  The report compares the scaling capabilities of 3DSFET with FinFET and GAA MBCFET, focusing on the contribution of a 42 nm gate pitch and three-layer nanosheet channels to advanced logic density.

• Process validationKey module integration validation

  Validate epitaxy, interlayer isolation, gate-metal patterning, and common source/drain contacts separately, and then assess the feasibility of full-flow integration.

  Structural analysis uses TEM, EDS, and other methods to confirm N/P metals and the stacked structure, while electrical testing is used to confirm whether the top devices and through contacts function properly.

• Electrical characterizationWafer-level device distribution analysis

  Identify process weak points through device survival rate, subthreshold swing, leakage, and threshold-voltage distribution.

  The report observes relatively good uniformity in overall current and leakage, but n-FET leakage and p-FET linear threshold voltage still show significant dispersion, which is further linked to source/drain epitaxy and bottom inner gate-length issues.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• Samsung Electronics

  Technology R&D entity and potential beneficiary company

  Strengths

  It has demonstrated a 3DSFET with a 42 nm gate pitch and three-layer nanosheets in both the upper and lower tiers, and has integration and characterization capabilities for multiple key modules.

  Weaknesses

  The survival rate of the common source/drain structure is approximately 40%, some leakage and threshold-voltage dispersion remain significant, and inverter and SRAM validation has not yet been completed.

  Comparison

  Compared with the 48 nm, 2/2 nanosheet schemes demonstrated by Samsung at VLSI 2024 and VLSI 2025, this work reduces the pitch to 42 nm and increases the channel stack to 3/3 layers, but the completeness of circuit functionality is currently lower.

  Risks

  The transition from experimental devices to stable mass production still requires solutions to issues including yield, process window, parasitic parameters, thermal management, design ecosystem, and manufacturing cost.

Key data

• Gate pitch42 nmThe report describes it as the most aggressive pitch among the demonstrated schemes at the time.
• Nanosheet channels3 layers at the top, 3 layers at the bottomThe previous comparison scheme used 2 layers at the top and 2 layers at the bottom.
• Gate lengthLess than 15 nmThis work is consistent with the target for future work.
• Target cell heightLess than 100 nm3DSFET is used to extend standard-cell height scaling.
• Top NMOS on/off ratioGreater than 10^7It also achieved a device survival rate of over 95%.
• Common source/drain subthreshold swing75 mV/dec for n-FET and 73 mV/dec for p-FETThe device survival rate for this structure is approximately 40%.
• Current circuit functionalityN/P transistors have been validated, while inverters and SRAM have not yet been validatedInverters and SRAM are included in future work.

Impact & implications

If the 42 nm gate-pitch 3DSFET can further improve yield and complete circuit-level integration, this architecture is expected to become an important candidate for extending advanced logic density scaling after GAA, and would be positive for Samsung Electronics' advanced process R&D capabilities. Validation of through contacts, interlayer dielectric isolation, and vertical gate-metal patterning also provides a foundation for reducing interconnect resistance and capacitance and improving design flexibility. However, this report only demonstrates the feasibility of early-stage devices and modules, and is not yet sufficient to infer mass-production timing, cost, performance-power advantages, or financial contribution.

Risks

• Incomplete epitaxial growth in the top source/drain region may form leakage paths, leading to greater dispersion in n-FET off-state current.
• The bottom inner gate length changes gradually from top to bottom, which may cause fluctuations in p-FET linear threshold voltage.
• The device survival rate of the common source/drain structure is approximately 40%, still showing a clear gap versus manufacturability and mass-production requirements.
• The current scheme has not yet implemented gate isolation, complete backside contact, inverters, or SRAM, and circuit-level usability has not yet been proven.
• The report does not provide performance, power consumption, area, cost, or mass-production timetable, making it impossible to quantify commercialization value.
• Three-dimensional stacking may increase process complexity, thermal coupling, parasitic effects, and the difficulty of yield control.

What to watch

• Progress in improving top source/drain epitaxial quality and bottom source/drain vertical etching.
• Whether the device survival rate of the common source/drain structure and the complete 3DSFET flow can improve significantly.
• Whether gate isolation, differentiated work-function metals, and backside contacts can be integrated.
• Validation results for the functionality, performance, power consumption, and area of inverters and SRAM.
• Intra-wafer and inter-wafer uniformity of the 42 nm gate-pitch scheme.
• Whether this technology enters the advanced logic process roadmap and discloses mass-production nodes and timeline.