AI chip upgrades push semiconductor testing into a core position

Overview

This report focuses on advanced semiconductor testing. Nomura extends its previously positive view on semiconductor OSATs to Taiwan-based test interface and test equipment companies. The core logic is that AI chips and advanced packaging increase the value of back-end processes, and testing, as a key gate to reduce downstream failures, is rising in importance, duration, hardware specifications, and strategic supply-chain value.

Core views

The report’s core view is that testing is now in the driver’s seat. Greater AI/HPC chip complexity, larger package sizes, higher pin counts, finer pitch, higher power consumption, higher current, high-speed/high-frequency signals, and thermal management requirements naturally lengthen testing flows and drive additional insertion points such as earlier KGD, BIT, and SLT. Hardware such as test equipment, probe cards, sockets, handlers, and test interface boards must be upgraded, and key suppliers have stronger pricing power and order visibility in a supply-constrained environment.

Analysis framework

The report forms its industry view through supply-chain analysis, a breakdown of nVidia GPU generational testing time, a review of CPO testing insertion flows, the impact of advanced packaging on back-end value, and a comparison of the testing hardware market structure and Taiwan-based vendors, and combines this with company coverage ratings to provide investment recommendations.

Methodology notes

• Industry chain analysisAI chip test content breakdown

  Break down testing time and cost mix by FT, BIT, and SLT

  Using nVidia Hopper, Blackwell, and Rubin as examples, the report estimates the increase in Final Test, System-Level Test, and Burn-in Test time resulting from generational upgrades, and derives the rise in test content cost as a percentage of manufacturing cost.

• Technology roadmap analysisCPO testing insertion flow

  A multi-stage process from EIC/PIC wafer testing to OE and module-level testing

  The report breaks CPO testing into about 4 to 5 insertion points, including single-sided wafer-level testing, double-sided wafer-level electro-optical testing after hybrid bonding, post-dicing OE testing, pre- and post-packaging testing, and module-level testing, to assess new equipment and interface demand.

• Supply chain comparisonPositioning comparison of testing hardware vendors

  Differentiate beneficiary segments across OSAT, test interfaces, test equipment, and consumables

  The report compares the roles of Taiwan-based companies such as MPI, WinWay, Hon Precision, Chroma, ASE, and KYEC within the advanced testing theme, and highlights order spillover, market share gains, and tight supply.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• ASE (3711 TT)

  OSAT beneficiary; report reiterates Buy

  Strengths

  Can participate in back-end CPO insertion points; SPIL is seen by the report as likely a major early service provider; benefits from advanced packaging and increased test content.

  Weaknesses

  There is still uncertainty around CPO mass-production ramp-up, customer selection, and process visibility.

  Comparison

  Compared with pure test interface or equipment vendors, ASE is more focused on back-end services and OSAT capabilities.

  Risks

  Slower AI demand, cuts in customer capex, delayed or reduced capacity expansion.

• KYEC (2449 TT)

  OSAT/testing service beneficiary; report reiterates Buy

  Strengths

  Benefits from longer AI chip testing time, incremental BIT and SLT demand, and order spillover.

  Weaknesses

  Sensitive to the pace of AI chip upgrades and customer expansion plans.

  Comparison

  Like ASE, it belongs to the testing services chain, but with a different customer mix and project pipeline.

  Risks

  Slower new product migration and lower-than-expected growth in test content.

• MPI (6223 TT)

  Test interface beneficiary; report initiates coverage with Buy

  Strengths

  Positioned in the probe card and test interface upgrade trend, benefiting from fine pitch, MEMS probes, and advanced packaging testing demand.

  Weaknesses

  Adoption of high-specification products depends on customer designs, equipment choices, and certification timing.

  Comparison

  Like WinWay, it is a key beneficiary in test interfaces, though product mix and customer programs may differ.

  Risks

  Unsettled CPO processes, changes in supplier selection, intensifying competition.

• WinWay (6515 TT)

  Test interface beneficiary; report initiates coverage with Buy

  Strengths

  Benefits from upgrades in socket, high-speed/high-frequency, high-current, and thermal management specifications, as well as visibility on AI project orders.

  Weaknesses

  Valuation and earnings elasticity may be affected by customer concentration and project timing.

  Comparison

  Together with MPI, it represents Taiwan’s beneficiary chain in test interfaces.

  Risks

  AI demand below expectations, slower customer capacity expansion, delayed pace of specification upgrades.

• Hon Precision (7769 TT)

  Test equipment beneficiary; report initiates coverage with Buy

  Strengths

  Benefits from rising demand for handlers, thermal control, multi-zone temperature control, larger trays, and customization.

  Weaknesses

  Equipment shipments typically lead mass production, so changes in customers’ production schedules may affect order conversion.

  Comparison

  Compared with Chroma, business overlap is limited; the report says the two have relatively little overlap in business scope.

  Risks

  Delays in capacity expansion plans, changes in equipment selection.

• Chroma (2360 TT)

  Test equipment beneficiary; report resumes coverage with Buy

  Strengths

  Benefits from ATE, test systems, and demand for high-specification testing; CPO electro-optical co-testing may create incremental equipment demand.

  Weaknesses

  Some innovative products are still in incubation, and the actual ramp-up pace remains uncertain.

  Comparison

  Business overlap with Hon Precision is limited, with each serving different parts of the test equipment chain.

  Risks

  Uncertainty in CPO or advanced packaging test flows, slower-than-expected demand realization.

Key data

• Report date2026-07-24The page shows Global Markets Research 24 July 2026.
• Final Test time index from Hopper to Blackwell1x至4xUsing Hopper FT time as 1, the report estimates Blackwell at 4x.
• Final Test time index from Hopper to Rubin1x至约7xUsing Hopper FT time as 1, the report estimates Rubin at about 7x.
• System-Level Test time indexBlackwell 1.5x，Rubin 2.5xUsing Hopper SLT time as 1.
• Test content cost ratioHopper 1.9%，Blackwell 2.5%，Rubin 3.3%Test content is defined as the sum of FT, BIT, and SLT.
• TSMC COUPE performance targetSubstrate CPO vs. copper interconnect: 4x energy efficiency and 10x latency improvement; interposer solution can reach 10x energy efficiency and 20x latency improvementThe report cites TSMC’s description of COUPE/CPO.
• Share of advanced high-performance packagingLess than 2% of total IC shipment units in 2024The report cites related forecasts from Yole, with subsequent growth potential viewed as an important driver.

Impact & implications

If the report’s view proves correct, AI chip testing will be upgraded from a traditional back-end supporting step to a key bottleneck that determines yield, reliability, and mass-production cadence. Longer testing time and upgraded hardware specifications will increase the value of test interfaces, probe cards, sockets, handlers, ATE, and OSAT services; CPO could also open incremental markets such as electro-optical co-testing and double-sided testing. From an investment perspective, Taiwan-based companies with key customer programs, capacity expansion, and high-specification testing capabilities should benefit more.

Risks

• Weaker hyperscaler capex outlook and softer AI-related commentary.
• An overall slowdown in AI demand, or AI commercialization progressing below expectations.
• A slower pace of new product migration and upgrade cycles, limiting growth in testing value.
• Delayed or reduced capacity expansion plans.
• CPO testing flows, yield, supplier selection, and equipment choices are still not fully determined.

What to watch

• Mass-production cadence and changes in testing time for nVidia Blackwell, Rubin, and subsequent platforms.
• Actual ramp-up, yield, and stabilization of testing flows for CPO/SiPh starting from 2H26E.
• Progress of TSMC COUPE, 200G/400G modulators, and the CPO roadmap.
• Capacity expansion plans and order visibility of OSAT, test interface, and test equipment vendors.
• Adoption speed of MEMS probes, coaxial sockets, thermal-control handlers, TIBs, and external high-frequency/optical measurement equipment for ATE.