AMD's acquisition of Taalas expands its differentiated AI inference stack, while memory and analog chip cycle signals improve simultaneously

Overview

This report focuses on three themes: the implications of AMD's acquisition of Taalas for differentiated AI inference architecture, storage technology trends presented at the Future of Memory Storage conference, and the recovery progress shown in the latest earnings season for analog semiconductor companies. UBS believes Taalas's approach of hardwiring model weights into silicon can reduce data movement more thoroughly than traditional GPUs and some SRAM-centric architectures, thereby expanding AMD's custom computing capabilities. In storage, persistent KV Cache demand, CXL memory pooling, and HBF could all increase the value of storage capacity. In analog chips, improving demand from industrial, data center, and automotive markets, together with price increases, is driving a rebound in industry revenue forecasts.

Core views

First, Taalas directly encodes fixed model parameters into silicon, eliminating weight reads during inference and making it suitable for inference workloads where models are stable and deployment scale is large; AMD can leverage its chip R&D, supply chain, and customer relationships to scale the technology. Second, KV Cache generated by AI inference could become an important incremental driver of NAND demand, while suppliers' new cleanroom capacity may be allocated first to HBM and DDR, making it difficult for NAND supply expansion to match potential demand. Third, CXL memory pooling is expected to improve memory utilization and extend the lifecycle of traditional technologies such as DDR4, while optically interconnected disaggregated memory could break through rack boundaries. Fourth, the analog chip industry has shifted from bottoming to recovery; analog chip revenue excluding MCUs is already above its long-term trend line, but MCU recovery is relatively lagging. Fifth, UBS continues to list TXN as its preferred name in analog chips, citing the combined advantages of share gains and fixed-cost leverage in a strong upcycle.

Analysis framework

The report combines analysis of M&A technology architecture, industry conference research, suppliers' theoretical performance models, company earnings versus consensus expectations, revenue revisions by end market and product, and comparisons of historical revenue trend lines and cyclical drawdowns. At the company valuation level, it uses methods including price-to-earnings ratio, next-twelve-month price-to-earnings ratio, and enterprise value to free cash flow multiples.

Methodology notes

• technology architecture analysisAI inference memory hierarchy and data movement analysis

  comparison of external HBM, on-chip SRAM, and model-weight hardwiring into silicon architectures

  Traditional GPUs need to repeatedly read model weights from external HBM. SRAM-centric architectures can reduce data movement, but weights still exist as stored data; Taalas goes further by converting fixed weights into transistor structures, thereby eliminating weight reads and freeing SRAM for dynamic inference tasks.

• industry cycle analysisrevenue trend line and cyclical drawdown analysis

  assessing the recovery stage based on where end-market and product revenue sit relative to long-term trends

  The report compares the peaks, drawdowns, and positions relative to long-term trend lines for automotive, industrial, analog chips excluding MCUs, and MCU revenue to measure the pace of recovery across segments.

• relative valuationprice-to-earnings ratio and next-twelve-month price-to-earnings ratio

  evaluating company value using earnings forecasts and comparable valuation multiples

  The report states that it uses a price-to-earnings methodology for some covered companies and uses next-twelve-month P/E to evaluate ADI; this method is sensitive to earnings forecasts, macro cycles, and changes in end demand.

• cash flow valuationenterprise value to free cash flow multiple

  evaluating companies using enterprise value relative to free cash flow

  UBS uses an enterprise value to free cash flow multiple to evaluate TXN, focusing on capital investment, free cash flow capability, and cyclical demand.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• US.AMD

  core company and acquirer of Taalas

  Strengths

  Has chip design R&D, supply chain scale, customer relationships, and diversified computing platforms, enabling it to incorporate Taalas technology into a more complete custom AI inference product portfolio.

  Weaknesses

  Model-specific chips are less flexible than general-purpose GPUs; each new model typically requires a new chip, and commercialization scale and iteration speed remain to be validated.

  Comparison

  Compared with traditional GPUs, the Taalas solution can eliminate weight reads from external memory; compared with SRAM-centric solutions, it further hardwires model weights into silicon structures.

  Risks

  Technology integration, customer adoption, rapid model iteration, chip tape-out cycle, cost-effectiveness falling short of expectations, and progress in competing architectures.

• SNDK

  important beneficiary mapping for KV Cache and HBF themes

  Strengths

  Puts forward an assessment of large-scale capacity demand for persistent KV Cache and demonstrates the potential of HBF to improve GPU utilization and capital efficiency.

  Weaknesses

  The related capacity and performance results are mainly based on estimates and theoretical modeling, and the scale of commercial deployment has not yet been validated.

  Comparison

  The HBF solution uses higher storage capacity to reduce spillover into slower system DRAM, achieving throughput close to that of 8 HBM-only GPUs with 4 GPUs in the example.

  Risks

  Undisclosed key demand assumptions, changes in AI workload architecture, product rollout delays, NAND price cycles, and supply response exceeding expectations.

• MRVL

  CXL memory pooling and optically interconnected disaggregated memory positioning

  Strengths

  Has deployed CXL solutions and is exploring the use of Celestial AI-related technology to enable optically interconnected memory across racks; its internal SRAM intellectual property is said to have high bandwidth per unit area.

  Weaknesses

  Disaggregated memory and optical interconnect solutions are still in development, with complex system integration and customer deployment.

  Comparison

  CXL memory pooling can improve memory utilization and may extend the useful life of traditional memory technologies such as DDR4.

  Risks

  Standards evolution, deployment pace, interoperability, hyperscaler in-house competition, and fluctuations in capital expenditure.

• TXN

  UBS's preferred name in analog chips

  Strengths

  Market share gains and fixed-cost leverage are expected to jointly drive earnings improvement during a strong industry upcycle.

  Weaknesses

  Capital investment levels are relatively high, and the business is sensitive to cyclical end-demand and pricing changes.

  Comparison

  Among the analog chip companies covered by UBS, TXN's CY26E revenue forecast revision is among the leaders.

  Risks

  Technological change, intense competition, capital expenditure pressure, pricing pressure, and cyclical fluctuations in end markets.

Key data

• potential persistent KV Cache capacityabout 1ZBSNDK's estimate for C2030; the report notes that key assumptions such as concurrent session retention time, cache miss rate, token speed, and KV size per token have not yet been disclosed.
• KV Cache relative to industry supply scalemore than 70% of C2027E industry bit supplyDerived from SNDK's estimate of persistent KV Cache, reflecting potential demand scale rather than confirmed orders.
• HBF equivalent throughput configuration4 HBF GPUs are roughly equivalent to 8 HBM GPUsFrom SNDK's preliminary theoretical modeling for agentic AI workloads; the HBM-only solution is constrained because the model spills over into slower system DRAM.
• HBF capital efficiencyup to about 8xThe theoretical improvement described by SNDK at the level of the minimum runnable configuration.
• HBF GPU efficiencyabout 2xThe theoretical improvement in GPU efficiency at similar token throughput.
• analog chip 2Q revenue beat1.7%Aggregated result for companies that have reported earnings.
• analog chip 3Q revenue expectation revision1.6%Aggregated result for companies that have reported earnings.
• analog chip annual revenue forecast adjustmentCY26 about +1.5%; CY27 about +3%Magnitude of full-year forecast revisions described in the report body.
• industrial and automotive revenue relative to long-term trendboth about 7% belowIndustrial revenue previously peaked in 1Q23, and automotive revenue peaked in 4Q23; both have now recovered significantly.
• MCU revenue relative to long-term trendabout 13% belowMCU peaked in 3Q23, and its current recovery lags products excluding MCUs in analog chips.

Impact & implications

For AMD, the strategic value of acquiring Taalas mainly lies in supplementing dedicated inference capabilities for fixed models and large-scale deployment scenarios, rather than immediately replacing general-purpose GPUs. If the technology can be scaled with AMD's R&D, supply chain, and customer channels, the company can form a broader product portfolio covering general-purpose GPUs, disaggregated inference, and model-specific chips. For the storage industry, growth in KV Cache capacity may increase the importance of NAND and high-capacity storage, while CXL and HBF are expected to improve memory utilization and GPU capital returns. For the analog chip industry, cyclical recovery, long-term data center growth, and pricing improvement jointly support upward revenue revisions, but MCU and some industrial and automotive demand have not yet fully returned to long-term trends.

Risks

• The Taalas architecture requires chips to be redesigned for new models, which may make it difficult to adapt to scenarios with rapid model iteration or insufficient demand scale.
• The transaction value, integration plan, product timeline, and financial impact of AMD's acquisition were not disclosed in the provided content.
• SNDK's forecast of about 1ZB of persistent KV Cache demand lacks multiple key parameters, and actual demand could be significantly lower than estimated.
• Capacity allocation among HBM, DDR, and NAND may change, and supplier capacity expansion or improvements in technical efficiency could weaken expectations for NAND supply-demand tightness.
• Analog chip demand remains affected by the macro economy, industrial activity, and the pace of automotive and EV adoption, while MCU recovery is clearly lagging.
• International trade disruptions, technological disruption, intensified competition, pricing pressure, and high capital investment may affect industry revenue and valuations.
• The HBF results in the report are preliminary theoretical modeling and do not mean that actual mass-produced systems will necessarily achieve the same efficiency.

What to watch

• AMD's integration path for Taalas, the tape-out timing of the first product, the range of supported models, and customer adoption.
• Actual performance per watt, cost, and deployment flexibility of model-specific inference chips relative to GPUs and large-capacity SRAM architectures.
• Core assumptions for persistent KV Cache, such as session retention time, cache miss rate, token speed, and KV size per token.
• The allocation order of new cleanroom capacity among HBM, DDR, and NAND by NAND suppliers, and price changes.
• Progress in CXL memory pooling, optically interconnected disaggregated memory, and HBF from theoretical models to commercial deployment.
• Subsequent orders, inventory, price increases, and demand trends in industrial, automotive, and data center markets for analog chip companies.
• The pace of MCU revenue recovery relative to its long-term trend, and the realization of TXN's share gains and fixed-cost leverage.