AI Demand Drives Up HBM and DRAM Prices, While In-Memory Computing Could Reshape the Long-Term Memory Bottleneck

Overview

This report discusses how AI is driving demand, prices, and revenue growth for HBM and DRAM, and analyzes potential changes in memory architectures as AI shifts from training to inference. Its core conclusion is that the current shortage stems from stronger-than-expected demand, high HBM wafer consumption, and slow supply expansion; long-term solutions include algorithmic optimization, HBM base dies, custom memory, and in-memory or near-memory computing.

Core views

The report first attributes the current strength in AI memory to expanding capital expenditure by hyperscale data centers. AI-related spending is exceeding previous expectations, while computing systems require extremely high memory bandwidth. Consequently, demand growth is reflected not only in greater storage capacity but also in concentrated demand for high-bandwidth products. On this basis, the report identifies AI spending, bandwidth requirements, and supply constraints as the three main drivers of the DRAM shortage. HBM's impact on the supply side is particularly significant. The report states that HBM occupies approximately three times the die area of DDR and therefore consumes more available capacity for the same wafer input. Meanwhile, DRAM wafer output has remained essentially stagnant for more than 10 years, and installing additional capacity takes more than 2 years, meaning supply cannot respond rapidly to AI demand. The combination of rapidly rising demand and slow supply expansion has created a memory shortage and intensified upward pressure on prices. This supply-demand mismatch is already reflected in the industry's revenue composition. The report uses the heading “Record Memory Revenue $200,” but the provided text does not specify the unit of this figure. It also explicitly states that most growth comes from prices rather than simply from shipment expansion. This means the key mechanism behind current revenue growth is improved pricing caused by tight supply, while HBM's high consumption of wafer resources further affects the supply and pricing dynamics of conventional DRAM. The long-term pattern of demand will change as AI expands from training into inference. The report notes that inference resource requirements span a broad range: low-end applications may require only microcontrollers, while large language models remain at the high end, supported by hyperscale data centers. Computing power, bandwidth, and cost requirements vary substantially across inference scenarios, so no single memory solution will cover all AI workloads in the future. The report also cautions that the current data-movement problem may not persist in its present form indefinitely. Algorithms continue to improve, potentially reducing today's pronounced data-movement pressure. Meanwhile, in-memory and near-memory computing can reduce data transfers between processors and memory, providing another path to alleviating the “memory wall.” The report therefore describes the memory wall in 2026 as “looking different.” The point is not that the bottleneck will disappear entirely, but that workload composition, algorithms, and hardware solutions will jointly change its form. Specific technological directions include using HBM base dies to incorporate more logic functions, adopting custom memory chips to improve performance, and using analog neural networks in low-end applications. The report believes these approaches could reduce data traffic and alleviate the memory wall, but current software support remains weak and constrains the adoption of new architectures. The underlying logic is that hardware capabilities alone are insufficient to achieve an architectural transition; toolchains and software ecosystems must mature in parallel. Over the longer term, the report expects AI to gradually become “invisible,” meaning it will be integrated into everyday systems rather than perceived as a standalone feature. AI may also lower application costs and lead users to make continuous use of agents. The report compares this process to the early adoption of semiconductors, microprocessors and microcontrollers, and the internet, indicating that its outlook focuses not only on HBM demand from data centers but also on changes in memory demand as AI spreads to a broader range of endpoints and cost tiers.

Analysis framework

The report first explains demand growth through hyperscale data center capital expenditure and AI bandwidth requirements, then analyzes shortages and price transmission by considering HBM's die area relative to DDR, DRAM wafer supply, and capacity expansion lead times. It subsequently examines workload changes from training to inference, compares resource requirements across computing tiers, and discusses solutions for alleviating data-movement bottlenecks, including algorithmic optimization, HBM base dies, custom memory, analog neural networks, and in-memory or near-memory computing, before extending the analysis to AI's long-term adoption path.

Methodology notes

• Industry/Sector Analysis FrameworkSupply-demand framework

  AI Memory Supply-Demand Analysis

  The report treats stronger-than-expected AI spending and high-bandwidth requirements as demand drivers, while viewing the long-term constraints on DRAM wafer supply and the capacity expansion cycle of more than 2 years as supply constraints. It uses the mismatch between the two to explain shortages and price increases.

• Industry/Sector Analysis FrameworkVolume-price decomposition

  Volume-Price Decomposition of Memory Revenue Growth

  The report explicitly states that most revenue growth comes from prices, thereby distinguishing the contributions of higher pricing and shipment growth to record memory revenue.

• Industry/Sector Analysis FrameworkUpstream-Midstream-Downstream Industry Chain Transmission

  Transmission from Data Center Capital Expenditure to Memory Prices

  The report explains the industry-chain impact through the sequence of hyperscale data center AI investment, computing-system bandwidth requirements, HBM wafer consumption, tightening DRAM supply, and rising memory prices.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• HBM

  A primary beneficiary technology of AI's high-bandwidth demand and an important source of pressure on DRAM wafer supply.

  Strengths

  It can meet the bandwidth requirements of high-end AI systems and use base dies to incorporate more logic functions.

  Weaknesses

  It occupies approximately three times the die area of DDR, resulting in higher costs and wafer consumption.

  Comparison

  Compared with DDR, HBM requires approximately three times the die area.

  Risks

  Algorithmic improvements may reduce data-movement pressure, while insufficient software support may also limit the adoption of new HBM architectures.

• DRAM

  HBM's high wafer consumption and AI demand jointly tighten overall DRAM supply and drive prices and industry revenue higher.

  Strengths

  It remains an essential memory foundation for computing systems ranging from low-end to high-end.

  Weaknesses

  Wafer output has remained essentially stagnant for more than 10 years, and installing additional capacity takes more than 2 years.

  Comparison

  DDR has a smaller die area than HBM, but shares constrained DRAM wafer resources with HBM.

  Risks

  Slow supply expansion may prolong the shortage, while algorithmic and architectural changes may alter the long-term demand structure.

• In-Memory and Near-Memory Computing

  Alleviates the memory wall by reducing data movement between processors and memory.

  Strengths

  It can use HBM base dies, custom memory, or 3D DRAM architectures to improve data-processing efficiency.

  Weaknesses

  Current software support is weak, representing a key constraint on adoption.

  Comparison

  Compared with the traditional model of separating processors and memory, its goal is to perform more computation near where the data resides.

  Risks

  If the software ecosystem does not mature in parallel, hardware solutions may be difficult to deploy at scale.

Key data

• HBM Die Area Relative to DDR3XThe report states that HBM occupies approximately three times the die area of DDR and therefore consumes more wafer capacity.
• Period of Stagnant DRAM Wafer Output>10 yearsThe report states that DRAM wafer output has remained essentially stagnant for more than 10 years.
• Additional Capacity Installation Cycle>2 yearsNew capacity takes more than 2 years from construction to installation, making it difficult for supply to respond rapidly to demand.
• Memory Revenue$200The report heading describes this as a record level, but the provided content does not specify the unit.
• Source of Revenue GrowthMostly from pricesThe report believes growth is driven primarily by pricing rather than solely by shipment growth.
• Range of Inference ResourcesMicrocontrollers to hyperscale data centersLow-end inference can be handled by microcontrollers, while large language models still require the highest-end data center resources.

Impact & implications

The report believes that HBM's higher wafer consumption transmits AI demand to overall DRAM supply and prices, making current memory revenue growth more dependent on pricing. As AI workloads expand into inference, the market will require both low-cost endpoint solutions and high-end data center solutions. Algorithmic improvements and in-memory or near-memory computing may reduce data traffic, but their actual impact will depend on whether the software ecosystem can close existing gaps.

Risks

• Continued algorithmic improvements may gradually reduce the currently pronounced data-movement problem, thereby changing long-term demand for high-bandwidth memory.
• Software support for in-memory or near-memory computing is currently weak, constraining technological adoption.
• Installing additional DRAM capacity takes more than 2 years, and the slow supply response may prolong the shortage.

What to watch

• Monitor changes in memory and bandwidth requirements across device tiers as AI workloads shift from training to inference.
• Monitor developments in adding logic functions to HBM base dies, custom memory, and in-memory or near-memory computing.
• Monitor whether the relevant software toolchains improve enough to remove adoption bottlenecks for new memory architectures.
• Monitor whether algorithmic optimization materially reduces data-movement requirements.
• Monitor the installation progress of additional DRAM capacity and its supply release cycle of more than 2 years.