AI chip upgrades push semiconductor testing to the core of the supply chain
AI summary card
AI chip upgrades push semiconductor testing to the core of the supply chain
Nomura is bullish on the increases in testing time, testing content, and hardware specification upgrades driven by advanced packaging, CPO, and rising AI/HPC chip complexity, and believes Taiwan testing equipment and interface vendors will benefit from order spillover and supply constraints.
- From Hopper to Blackwell and Rubin, the share of testing time and testing cost in AI GPUs is expected to rise significantly, with testing content cost as a percentage of total cost increasing from 1.9% for Hopper to 2.5% for Blackwell and 3.3% for Rubin.
- Advanced packaging, chiplets, hybrid bonding, and multi-chip systems create a yield cliff, making KGD and earlier-stage testing more critical and driving higher complexity in CP, FT, BIT, and SLT.
- The CPO/SiPh testing process may form 4 to 5 test insertion points, involving wafer-level, die-level, package-level, and module/system-level testing, creating new markets for equipment, probe cards, sockets, and handlers.
- The report initiates coverage on MPI, WinWay, and Hon Precision with Buy, resumes coverage on Chroma with Buy, and reiterates Buy on ASE and KYEC.
Report interpretation
Overview
This report focuses on the advanced semiconductor testing supply chain, with the core view that AI chips, advanced packaging, and CPO have increased the importance of testing. As chip complexity, package size, pin count, fine pitch, power consumption, and thermal management requirements rise, testing workflows are expanding from traditional CP/FT to more complex BIT, SLT, and electro-optical co-testing, potentially increasing the value of test equipment, test interfaces, probe cards, sockets, handlers, and OSAT vendors.
Core views
Nomura believes the current AI cycle has not yet peaked, and the testing supply chain is shifting from a back-end supporting link to a key bottleneck and quality gatekeeper. Investment themes include increasing testing process complexity, more test insertion points, hardware specification upgrades, order spillover, share gains, and improved pricing power from supply constraints. Taiwan testing interface and equipment vendors already have project pipelines for multiple AI chip customers and strong order visibility.
Analysis framework
The report uses AI GPU generational evolution, advanced packaging cost structure, CPO testing workflows, testing hardware functional division, and comparisons of major Taiwan suppliers as its main framework to assess testing time, testing content cost, test insertion points, supplier positioning, and valuation. It focuses on comparing the roles of hardware such as ATE, prober/handler, probe card, socket, and test interface board in CP, FT, BIT, SLT, and CPO testing.
Methodology notes
FT, BIT, and SLT combined are defined as testing content cost, and the changes in their share of manufacturing cost across different AI GPU generations are compared.
Using nVidia Hopper, Blackwell, and Rubin as examples, the report estimates that testing time and testing cost share increase as product complexity rises.
CPO testing is broken down into EIC/PIC wafer-level testing, EPIC double-sided wafer-level testing, OE die/package-level testing, and module/system-level testing.
This framework is used to determine the equipment, test interfaces, and potential suppliers required at different stages, and to identify new opportunities brought by electro-optical co-testing.
When AI demand is strong and leading vendors face tight capacity, testing supply-chain vendors may gain share and stronger pricing power.
The report treats supply constraints, project pipelines, and capacity expansion plans as important indicators for judging order visibility.
Asset mapping & comparison
Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).
- ASE 3711 TTbeneficiary in AI OSAT
- Strengths
- The world's largest OSAT vendor; SPIL may play an important early role in back-end CPO testing.
- Weaknesses
- Implied upside from the target price is lower than that of other newly covered names.
- Comparison
- Compared with testing interface vendors, ASE is more of an integrated back-end packaging and testing service provider.
- Risks
- Slower AI demand, weaker customer capex, and capacity expansion progressing below expectations.
- KYEC 2449 TTbeneficiary in AI OSAT
- Strengths
- Optimized product mix and margin expansion support the Buy view.
- Weaknesses
- The business is still affected by AI testing demand and the pace of customer migration.
- Comparison
- Like ASE, it is in the OSAT chain, but differs in scale and business structure.
- Risks
- Slower new product migration, AI demand below expectations, and adjustments to expansion plans.
- MPI 6223 TTbeneficiary in test interfaces and probe cards
- Strengths
- Probe cards are the main source of revenue, and the company may also benefit from more CPO and advanced packaging test insertion points.
- Weaknesses
- Valuation is relatively high and sensitive to order conversion and technology adoption.
- Comparison
- Together with WinWay, CHPT, and Keystone, it forms the core group of Taiwan testing interface players.
- Risks
- Changes in customer selection, an unsettled CPO process, and intensified competition.
- WinWay 6515 TTbeneficiary in sockets and test interfaces
- Strengths
- Benefits from demand for high-performance sockets, thermal management, high speed, and high current capability.
- Weaknesses
- Market share migration and the pace of customer qualification may affect growth.
- Comparison
- Compared with MPI, it is more focused on sockets and test interfaces.
- Risks
- Specification upgrades below expectations, delays in customer adoption, and reduced AI order spillover.
- Hon Precision 7769 TTbeneficiary in FT/SLT handlers
- Strengths
- Has the highest implied upside in the table, benefiting from FT/SLT handler demand and longer AI testing workflows.
- Weaknesses
- Sensitive to capacity expansion and AI project progress.
- Comparison
- Compared with Chroma and MPI, Hon Precision is more focused on handler equipment.
- Risks
- SLT demand below expectations, delayed capacity expansion, and customer order adjustments.
- Chroma 2360 TTbeneficiary in test equipment and photonics testing
- Strengths
- Its positioning in power testing and semiconductor/photonics test equipment may benefit from CPO electro-optical testing.
- Weaknesses
- There is limited overlap with Hon Precision's business scope, and its growth depends more on demand for specific test equipment.
- Comparison
- Compared with handler vendors, Chroma is more focused on test equipment and photonics testing capabilities.
- Risks
- Slow CPO mass production, changes in equipment selection, and uncertainty in AI capex.
Key data
- coverage viewMPI 6223 TT, WinWay 6515 TT, and Hon Precision 7769 TT initiated with Buy; Chroma 2360 TT resumed with Buy; ASE 3711 TT and KYEC 2449 TT reiterated BuyThe stock action table shows the target prices and implied upside for the related companies.
- AI GPU final test time indexHopper=1, Blackwell about 4x, Rubin about 7xUsing nVidia AI GPUs as examples, the report estimates that FT test time rises significantly with generational upgrades.
- SLT test time indexHopper=1, Blackwell about 1.5x, Rubin about 2.5xSystem-level test time lengthens as AI chip complexity increases.
- testing content cost ratioHopper 1.9%, Blackwell 2.5%, Rubin 3.3%Testing content cost is defined as the sum of FT, BIT, and SLT.
- advanced packaging penetrationHigh-end performance packaging units accounted for less than 2% of total ICs in 2024 and may rise to about 5% by 2028EThe report cites Yole forecasts to show that advanced packaging remains small but is growing rapidly.
- advanced packaging growthHigh-end advanced packaging units 2024-2029E CAGR about 31%Growth in advanced packaging is driving higher testing intensity and greater value in back-end processes.
- yield cliff exampleIf 10 dies each have a 90% yield, final module yield is below 35%Under multi-chip integration, a single defect can amplify into the risk of scrapping an expensive package, increasing the importance of KGD.
- stock implied upsideASE 11%, Hon Precision 73%, Chroma 34%, MPI 33%, KYEC 32%, WinWay 28%Based on the closing prices and target prices in the table as of July 22, 2026.
Impact & implications
The investment implication of the report is that AI chip upgrades benefit not only wafer fabrication and packaging, but also significantly increase the value of the testing segment. Test equipment and interface vendors may see revenue growth, margin improvement, and valuation re-rating due to longer test times, higher specifications, more complex insertion points, and tight supply. CPO still faces uncertainty in processes and supplier selection, but once technological bottlenecks are overcome, it could create an entirely new incremental market for the testing ecosystem.
Risks
- Weaker hyperscaler capex outlook or more cautious commentary on AI investment.
- A broad slowdown in AI demand, or AI commercialization progress below expectations.
- Slower new product migration and upgrade cycles, limiting growth in testing value.
- Delays or cuts in capacity expansion plans.
- Significant uncertainty remains around CPO testing processes, yields, supplier selection, and equipment choices.
What to watch
- The mass-production pace of nVidia Blackwell, Rubin, and subsequent platforms, and changes in testing time.
- The actual ramp-up speed of CPO from 2026 onward, insertion-point design, and supplier qualification results.
- Progress in TSMC COUPE, 200G/400G MRM, and FAU roadmaps.
- Capacity expansion plans and order visibility of Taiwan vendors related to testing interfaces, handlers, probe cards, and ATE.
- Upgrade trends in TDP, package size, bump pitch, and PCB/interposer materials for AI/HPC chips.