Raised CoWoS Capacity Forecasts; Bullish on TSMC’s Long-Term Growth in Advanced Packaging

Overview

JPMorgan released a research report raising TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging capacity forecasts for 2027 and 2028. The report notes that accelerated growth in artificial intelligence (AI) computing demand—particularly from NVIDIA, AMD, and major cloud service providers (e.g., Google, AWS)—will drive significant expansion in TSMC’s advanced packaging business. Although progress on next-generation panel-level packaging technology CoPoS has lagged market expectations, TSMC remains well-positioned to meet high-performance computing demand over the coming years by expanding the maximum die size supported by existing CoWoS technology and accelerating adoption of 3D SoIC. Accordingly, the firm maintains its Overweight rating on TSMC and raises its target price to NT$2,500.

Core views

Broad Upward Revision of Capacity and Demand Forecasts: The report raises TSMC’s CoWoS monthly capacity forecasts for end-2026, 2027, and 2028 to 115K, 175K, and 220K wafers, respectively. Corresponding annual wafer output is projected to reach 1.1M wafers in 2026, 1.9M in 2027, and 2.4M in 2028. This revision reflects faster internal capacity ramp-up in 2027–2028 and enhanced ability to leverage outsourced semiconductor assembly and test (OSAT) partners and Vanguard International Semiconductor (VIS) for interposer manufacturing. Key Customer Dynamics and Product Roadmaps: For NVIDIA, rising compute demand from customers such as OpenAI has generated robust orders for Blackwell GB300; additionally, stronger-than-expected volume ramp of Spectrum X and Vera CPU in H2 2026 led to a modest upward revision of NVIDIA’s 2026 CoWoS demand forecast. While uncertainty around HBM4 supply prompted a slight downward adjustment to Rubin-series forecasts, the series is still expected to begin ramping in Q3 2026 and achieve scale production in Q4. Looking ahead to 2027, Rubin Ultra (a dual-die interconnect solution) and Vera CPU will continue driving growth, with Vera CPU potentially gradually outsourced to OSATs. For AMD, chip-level design issues with MI450 have been largely resolved, and mass production is expected to commence by end-2026. As a result, the firm significantly raises AMD’s 2027 CoWoS demand forecast to 180K wafers annually, reflecting strong MI450 ramp and Venice CPU demand. Separately, Broadcom and MediaTek see upward revisions to their CoWoS forecasts due to surging Google TPU demand; total TPU shipments are now projected at 4.5M units in 2026 and 8.0M in 2027. Technology Roadmap Evolution: CoWoS Longevity and SoIC Emergence: Compared to one or two months ago, TSMC’s progress on CoPoS (panel-level packaging) appears slower, and confidence among supply chain partners regarding CoPoS meeting NVIDIA’s requirements by H2 2028 has declined. In contrast, TSMC announced plans to expand the maximum CoWoS package size to 14 reticle sizes by 2028 (up from 8–9 previously), signaling a strategic decision to extend the CoWoS technology lifecycle amid CoPoS uncertainty. Meanwhile, growing cost challenges associated with larger packages are prompting TSMC to encourage customers to adopt chiplet-based designs and 3D SoIC packaging starting with the 2nm node. Starting in H2 2027, multiple ASICs—including Google’s TPUv9 and AWS’s Trainium 4—as well as select NVIDIA Feynman GPUs are expected to transition to 3D SoIC, driving strong SoIC capacity growth in 2028. Emerging Growth Drivers: CPUs, LPUs, and Networking Chips: Beyond GPUs, server CPUs (e.g., NVIDIA’s Vera and AMD’s Venice) adopting CoWoS packaging for the first time represent a new source of incremental demand. Additionally, Groq’s next-generation LPU (LP40) is expected to migrate from flip-chip to CoWoS-R packaging, while networking chips using CPO/NPO technologies face increased CoWoS demand due to larger package footprints. These applications—characterized by relatively lower packaging complexity and smaller die sizes—may become growth opportunities for OSATs.

Analysis framework

This report employs a bottom-up demand aggregation and capacity-matching analytical framework. First, it derives CoWoS wafer consumption estimates for key downstream customers (NVIDIA, AMD, Broadcom, MediaTek, AWS, etc.) by forecasting shipment volumes for specific product lines (e.g., Blackwell, Rubin, MI450, TPU). Second, it assesses whether TSMC’s own capacity build-out timeline—considering its technology roadmap (e.g., CoWoS size extension, SoIC adoption schedule) and supply chain dynamics (e.g., OSAT outsourcing ratios, CoPoS progress)—can satisfy this aggregated demand. Finally, it derives a target price using P/E valuation, incorporating expectations for improved utilization rates, higher average selling prices (ASPs), and gross margin expansion. This methodology emphasizes how specific product cycles directly pull upstream manufacturing capacity and how technology substitution paths reshape supply-demand fundamentals.

Methodology notes

• Industry/sector analysis frameworkSupply-demand framework

  Supply-demand balance analysis for advanced packaging capacity

  The report evaluates potential shortages or surpluses in advanced packaging capacity over the coming years by meticulously decomposing downstream AI chipmakers’ product roadmaps (demand side) and TSMC’s and its outsourced partners’ capacity expansion schedules (supply side), thereby inferring TSMC’s revenue growth potential and pricing power.

• Valuation methodologyPE/PEG valuation

  Forward P/E valuation

  The report applies a ~20x 12-month forward P/E multiple to derive the target price. This multiple exceeds TSMC’s five-year historical average, reflecting the firm’s premium valuation for anticipated gross margin improvement and accelerated growth.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• TSM.US (TSMC)

  Primary beneficiary: As the dominant supplier of CoWoS and SoIC, TSMC directly benefits from AI chip demand surge and capacity expansion.

  Strengths

  Technology leadership (CoWoS/SoIC), capacity exclusivity, strong pricing power, gross margin improvement outlook.

  Weaknesses

  Massive capital expenditures, geopolitical risk.

  Comparison

  Compared to Samsung and Intel, TSMC holds clear advantages in advanced packaging yield and customer ecosystem.

  Risks

  Debate over sustainability of AI capex cycle, weakness in PC/smartphone demand.

• AMD.US (AMD)

  Key customer: Volume ramp of MI450 and Venice CPU will significantly increase its consumption of TSMC’s CoWoS capacity.

  Strengths

  MI450 design issues resolved, improving product competitiveness; stable CPU business.

  Weaknesses

  AI GPU market share remains far below NVIDIA’s.

  Comparison

  Relative to NVIDIA, AMD’s CoWoS demand base is smaller but projected growth is faster (50% upward revision for 2027).

  Risks

  Integration challenges during rack-scale deployment, HBM supply constraints.

Key data

• TSMC CoWoS Monthly Capacity Forecast (end-2028)220K wafersRaised from prior expectation, reflecting accelerated internal capacity ramp and synergies from outsourcing collaboration
• TSMC CoWoS Monthly Capacity Forecast (end-2027)175K wafersSignificant year-on-year growth supporting continued AI chip volume ramp
• NVIDIA CoWoS Wafer Consumption Forecast (2027)1.12M wafers/yearDriven by Rubin series and Vera CPU; ~55% increase vs. 2026 forecast
• AMD CoWoS Wafer Consumption Forecast (2027)180K wafers/yearSharply raised, primarily reflecting strong MI450 series and Venice CPU demand
• TSMC SoIC Monthly Capacity Forecast (end-2028)65K wafersAccelerated adoption of 3D packaging, supported by new phase ramp at AP7 fab
• Target PriceNT$2,500Based on ~20x 12-month forward P/E, reflecting improved gross margins and faster growth

Impact & implications

For TSMC, advanced packaging has evolved from a complementary service into a structural growth engine. Persistent CoWoS capacity tightness and upward pricing trends will directly boost revenue and gross margins. Moreover, the technology roadmap shift toward larger CoWoS formats and 3D SoIC strengthens TSMC’s moat in leading-edge process nodes, making it difficult for competitors to enter the high-end segment with low-cost alternatives in the near term. For the broader supply chain, OSATs (e.g., ASE, Amkor) stand to gain opportunities in outsourced CPU and certain GPU packaging, but remain dependent on TSMC for the most advanced GPU packaging. For investors, this implies high visibility into TSMC’s earnings over the next several quarters and upside potential relative to consensus expectations.

Risks

• Duration of AI capex growth cycle remains contested; cloud provider spending cuts would directly impact demand
• Weak PC and smartphone demand in H2 2026 could negatively affect broader semiconductor recovery
• Slower-than-expected progress on CoPoS and other technologies may raise technology transition costs
• Potential geopolitical disruptions to supply chain stability

What to watch

• Confirmation of CoPoS final timeline at TSMC’s 2026 Technology Symposium
• Actual volume ramp timelines for NVIDIA’s Rubin series and AMD’s MI450
• Certification progress and market share gains for OSATs (e.g., ASE, Amkor) in CoWoS-L and CPU packaging
• Gross margin evolution and capacity utilization data for advanced packaging in TSMC’s quarterly earnings reports