SerDes Accelerates Toward 224G/448G; CPO/NPO Emerges as the Key Breakthrough for AI Networking

Overview

This report is the transcript of Nomura Securities’ 68th Global AI Trend Tracking Expert Conference Call, focusing on the latest developments of Serializer/Deserializer (SerDes) technology in AI high-speed interconnects. The session invited SerDes domain experts to systematically review technological specification evolution, upgrade timelines, the global competitive landscape, geopolitical policy impacts, and next-generation architectural directions (e.g., CPO/NPO), aiming to provide investors with professional insights into underlying communication technology transformations in AI infrastructure.

Core views

As a critical interface for high-speed interconnection between AI chips, SerDes performance directly constrains the scalability of AI cluster compute power. In current mainstream solutions, NRZ encoding is used below 56 Gbps, whereas PAM4 encoding is mandatory above 56 Gbps—requiring high-precision analog-to-digital converters (ADCs) and high-performance digital signal processors (DSPs) for signal processing. Technologically, the 112G solution has entered mass production; 224G is in early industrialization; and commercialization of 448G is projected to require another 3–5 years. Experts emphasize that, absent major breakthroughs in PCB substrates and advanced packaging materials, SerDes speed will likely hit its physical limit near 448G. To overcome this bottleneck, AI network architecture is accelerating toward co-packaged optics (CPO) and near-packaged optics (NPO), integrating optical engines directly into switches or servers to drastically reduce SerDes transmission distance and signal loss. Regarding competitive structure, the SerDes ecosystem comprises three types of players: First, system-level vendors such as Broadcom and Marvell, who develop SerDes in-house and deeply integrate them into proprietary chips; second, IP licensing firms such as Synopsys and Cadence, which supply SerDes design IP to third parties; third, vertically integrated tech giants such as NVIDIA and Huawei, embedding SerDes within their closed AI hardware ecosystems. Geopolitically, while the U.S. has not imposed explicit bans on SerDes end-products, it enforces export controls on high-end SerDes IP (e.g., from Synopsys and Cadence). China faces no significant bottlenecks in equipment or materials, but still lags notably in sub-7nm advanced process technology required for 224G-grade DSP chips—and in long-standing design capabilities.

Analysis framework

This report adopts a progressive industry analysis framework: 'technical parameters → upgrade timeline → physical constraints → architectural alternatives.' It first clarifies core SerDes metrics (NRZ vs. PAM4; dependency on ADC/DSP), then assesses lifecycle stages of successive generations (112G/224G/448G) based on production readiness; next identifies fundamental constraints limiting continued scaling (physical limits of PCBs and packaging materials), thereby naturally motivating the necessity and urgency of system-level solutions (CPO/NPO); finally, it dissects competitive barriers and practical challenges facing different participants by integrating supply chain division of labor and geopolitical policies—forming a complete logical chain from micro-level technology to macro-level industry structure.

Methodology notes

• Industry/Industrial Analysis FrameworkSupply-demand framework

  Although the report does not explicitly discuss quantitative supply-demand dynamics, it implicitly treats 'supply capability (i.e., SerDes speed ceiling)' as a binding constraint, reverse-engineering the inevitable evolutionary path of downstream AI network architecture

  When the supply side of a technology (e.g., SerDes speed) approaches its physical limit, robust downstream demand (e.g., for AI training clusters) forces system-level architectural innovation (e.g., CPO)—a classic example of supply-side constraints driving demand-side adaptation in industry analysis.

• Industry/Industrial Analysis FrameworkUpstream-Midstream-Downstream Industrial Chain Transmission

  The report clearly maps the full-chain transmission—from foundational IP (Synopsys/Cadence) → chip design (NVIDIA/Broadcom) → system integration (AI servers/switches) → final AI network applications

  By outlining SerDes’ position in the value chain, the report illustrates how upstream IP capability constraints directly affect midstream chip performance, ultimately restricting large-scale deployment of downstream AI networks—helping readers understand how technical bottlenecks cascade into broader industrial constraints.

• Cyclical & Sentiment FrameworkTechnology Iteration Cycle

  SerDes generational upgrade cycle (112G → 224G → 448G)

  Technology generation transitions are neither linear nor uniform, but follow an asymmetric cycle pattern of 'mass production → early innings → commercialization'; by labeling each generation’s current stage, this report signals structural investment opportunities tied to inflection points in technological advancement.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• NVIDIA CORP (NVDA.US)

  Vertically integrated SerDes integrator operating within a closed ecosystem; deeply couples SerDes into AI GPUs and networking chips, and stands to benefit directly from CPO/NPO architectural evolution

  Strengths

  Possesses a full-stack AI hardware ecosystem and strong chip-definition capabilities, enabling leadership in co-design of SerDes and optical interconnects

  Weaknesses

  Highly dependent on external advanced process nodes and packaging capacity, concentrating geopolitical supply-chain risk

  Comparison

  Compared with traditional communications chip vendors like Broadcom/Marvell, NVIDIA holds superior advantages in AI use-case definition authority and system-level optimization capabilities

  Risks

  Escalating U.S. export controls on high-end AI chips and associated technologies

Key data

• Mainstream Encoding Threshold56 GbpsNRZ used below this threshold; PAM4 required above it
• Current Mass Production Level112GHas entered Volume Production phase
• Next-Generation Primary Node224GCurrently in Early Innings phase
• 448G Commercialization Outlook3–5 yearsExpert-estimated time window
• Key Domestic Bottleneck for 224GSub-7nm Process NodeCorresponds to DSP chip manufacturing capability

Impact & implications

For the AI infrastructure supply chain, the plateauing of SerDes speeds implies that the traditional path of simply stacking interconnect bandwidth is no longer sustainable; CPO/NPO will become the core vehicle for AI network upgrades over the next 3–5 years—benefiting complementary segments including optical engines, silicon photonics, and advanced packaging. For China’s domestic semiconductor industry, the lack of high-end SerDes IP and DSP design capabilities highlights gaps in autonomous control over foundational AI interconnect technologies—and pinpoints key focus areas for domestic substitution. For leading AI chipmakers (e.g., NVIDIA), their vertical integration capabilities will be further strengthened under the trend of SerDes-optical interconnect convergence.

Risks

• CPO/NPO technology implementation falling short of expectations after SerDes physical speed limits are reached
• U.S. broadening export restrictions on SerDes-related IP, EDA tools, and advanced packaging equipment
• China’s persistent inability to break through sub-7nm DSP design and manufacturing, resulting in sustained lag in 224G+ SerDes products

What to watch

• Actual adoption timeline of 224G SerDes chips in mainstream AI accelerators and switches
• Testing feedback and scheduled large-scale deployment of CPO/NPO prototypes in major cloud providers’ AI clusters
• Tape-out and validation progress of 224G-level products by domestic SerDes IP vendors (e.g., SmartSens, Jiehua Tech)