IMEC improves CFET backside contact with Delta solution, reducing access resistance to 378 Ω·µm

Overview

The report presents an improved Delta integration scheme proposed by researchers from IMEC and ASM for monolithic CFET backside contacts. The study covers frontside source/drain and isolation structures, wafer bonding, extreme wafer thinning, backside dielectric isolation, and backside contact etching, focusing on solving issues in the existing flow such as eSiGe:B volume variation, fin silicon residue, wet-etch erosion, overlay error, and high access resistance.

Core views

The core value of the Delta solution lies in placing FS-BDI below the source/drain and combining it with low-temperature CDE eSiGe:B, optimized bonding, extreme wafer thinning, backside isolation, and contact etching to form a more robust backside contact path. Experimental results show that this flow not only improves the electrical performance of the bottom PMOS but also significantly increases device survival rate. If cross-wafer consistency, scaled yield, and manufacturing cost can be validated subsequently, this solution is expected to enhance the implementability of backside power delivery and vertically stacked transistors in advanced logic nodes.

Analysis framework

The study first compares the Beta and Delta structures and high-level process flows, then identifies bottlenecks such as eSiGe:B variation, fin silicon residue, and BDIC wet-etch erosion through failure analysis; it then separately optimizes frontside integration, bonding alignment, wafer thinning, backside isolation, and contact etching, ultimately validating the improvements through pFET survival rate, access resistance, and drive current.

Methodology notes

• structure scheme comparisonComparison of Beta and Delta schemes

  Compare the integration paths and contact performance of different CFET backside contact structures.

  Using the existing Beta scheme as a reference, the study focuses on evaluating the improvements of the Delta scheme in source/drain isolation, eSiGe:B stability, backside contact formation, and bottom PMOS performance.

• process integrationFrontside-to-backside full-flow validation

  Evaluate frontside device formation, bonding, thinning, backside isolation, and contact etching as a continuous process chain.

  This method emphasizes the dependencies among steps; for example, FS-BDI both performs sub-fin isolation and protects eSiGe:B during subsequent wet processing.

• failure analysisFailure-mode-driven optimization

  Adjust the process based on failure modes such as fin silicon residue, eSiGe:B erosion, and insufficient contact etching.

  The report locates issues through failure maps, morphology observations, and device survival rate, and improves wet-chemistry accessibility, material protection, and through-etching of SiOCN.

• electrical validationSurvival rate and access resistance evaluation

  Use device survival rate, access resistance, and drive current to measure process effectiveness.

  The pFET survival rate reflects the robustness of the integration flow, while access resistance and drive current directly measure the contribution of backside contact to bottom PMOS performance.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• IMEC mCFET Delta process platform

  direct research object of the report

  Strengths

  Both access resistance and device survival rate improved significantly, and the study covers a complete validation chain from frontside integration to backside contact.

  Weaknesses

  It remains at the R&D and experimental demonstration stage, lacking data on scaled manufacturing cost, long-term reliability, and mass-production cadence.

  Comparison

  Compared with the existing Beta scheme and previous results, the Delta scheme reduces eSiGe:B variation and improves bottom PMOS performance.

  Risks

  Experimental results may be affected by wafer batches, material uniformity, overlay control, and etching windows, and cannot yet be directly extrapolated to large-scale mass production.

• advanced semiconductor bonding, thinning, and selective etching value chain

  potential process beneficiary area

  Strengths

  CFET backside contact requires higher-precision bonding alignment, extreme wafer thinning, and material-selective etching capabilities.

  Weaknesses

  The report does not disclose equipment supply shares, per-wafer costs, or capital expenditure requirements.

  Comparison

  Advanced notch alignment reduced fingerprint defects compared with conventional mark alignment and achieved bonding overlay error of less than 100 nm.

  Risks

  CFET commercialization progress, process-route competition, and customer validation cycles may delay realization of related demand.

Key data

• access resistance1753→378 Ω·µmMeasurement result of the improved Delta backside contact scheme.
• drive currentapproximately 5x improvementThe report states that the decrease in access resistance brings an approximately 5x improvement in drive current.
• pFET survival rate45%→85%Compared with the previous report, the survival rate increased by 40 percentage points.
• bonding overlay errorless than 100 nmAdvanced notch alignment showed no fingerprint defects observed in conventional mark alignment.
• fin silicon residue failurefully resolved in the experimentThe report states that this failure issue was 100% resolved, though more batch data are still needed to verify repeatability.
• bottom source/drain epitaxy improvementapproximately 70%The report table mentions the bottom source/drain epitaxy improvement brought by cover spacer formation and CDE co-flow.

Impact & implications

The results indicate that backside contact is not merely a single etching step, but a systems engineering problem jointly determined by frontside isolation, epitaxial material control, bonding overlay, wafer thinning, and backside dielectric etching. If the Delta solution can achieve stable mass production, it may reduce the parasitic resistance of bottom devices in vertically stacked CFETs and enhance the density and performance potential of advanced logic nodes. At the industry level, it may benefit process demand for high-precision bonding, wafer thinning, selective etching, epitaxial deposition, and advanced metrology, but the report is not yet sufficient to quantify the revenue or profit impact on related companies.

Risks

• The report is a technical conference presentation and lacks mass-production scale, cross-batch uniformity, and statistical confidence intervals.
• It does not disclose complete reliability, thermal budget, long-term aging, or process window data.
• The complete resolution of fin silicon residue failure and the 85% survival rate both need to be reproduced on more wafers and under different process conditions.
• Extreme wafer thinning, bonding overlay, and multi-material selective etching may increase manufacturing complexity and cost.
• The report does not provide a commercialization timeline, customer adoption status, or financial impact on listed companies.
• BSC in this paper refers to backside contact and should not be mapped to the securities ticker BSC on this basis.

What to watch

• Whether the pFET survival rate can move closer to mass-production requirements and remain stable across batches.
• Whether the 378 Ω·µm access resistance and approximately 5x drive current improvement can be reproduced in larger samples.
• The process window for FS-BDI through-etching in terms of eSiGe:B landing control and material selectivity.
• The overlay accuracy, throughput, and defect rate of advanced notch alignment on mass-production bonding equipment.
• Mechanical stability, wafer warpage, and yield performance after extreme wafer thinning.
• Cost and performance comparison between the Delta solution and other CFET and backside power delivery integration routes.
• Whether IMEC, ASM, and industry partners subsequently disclose pilot production, reliability, or customer validation progress.