4F² Vertical-Gate DRAM Improves Retention and Sensing Margin Through Back-Gate and Bit-Line Shielding

Overview

The report examines the scaling and integration challenges of 4F² vertical-gate DRAM, sequentially covering the PUC architecture, data retention, junction engineering, shared back gates, bit-line shielding, and wafer thinning for POC architectures. It concludes that this integrated solution has demonstrated robust cell-transistor and read/write performance and has the potential to support future high-density DRAM.

Core views

The report first compares 6F² and 4F² solutions in terms of cost and process scalability. It concludes that vertical gates can support multiple generations of scaling beyond 10nm, although capacitors still require continuous improvement. Compared with buried gates, the table indicates that vertical gates face no SAC challenge, require fewer EUV steps than the reference solution, and deliver better cell efficiency when combined with PUC and Deck. Therefore, the 4F² vertical-gate approach is attractive in terms of area efficiency and process scaling. For device integration, the report adopts a PUC architecture for 4F² vertical-gate DRAM, combining vertical channels with fusion wafer bonding. Final validation results show that the architecture provides robust cell-transistor and read/write operations and is therefore considered promising for future high-density DRAM. This also forms the integration foundation for subsequent back-gate, bit-line shielding, and wafer-thinning technologies. Data retention is one of the architecture's main performance advantages. The report states that floating-body vertical-gate cells outperform conventional planar DRAM in data retention under all three operating modes: static standby, static active, and dynamic. Meanwhile, floating-body cells face a potential drop caused by hole accumulation, making gate-induced drain leakage (GIDL) and off-current (IOff) factors that need to be controlled. The report effectively controls GIDL through junction engineering and proposes jointly optimizing trap depth and junction depth to balance data retention and drive current. The shared back gate is used to address threshold-voltage and adjacent-word-line interference issues. The report validates that the shared BG can both adjust the threshold voltage Vth and suppress pass-gate electric-field interference caused by adjacent-word-line bias. However, this improvement is not cost-free: Vth control and pass-gate-effect suppression must be balanced against subthreshold swing SS and on-current Ion. The report considers the associated Ion/SS trade-off to remain acceptable. As cells shrink to 4F², parasitic capacitance between adjacent bit lines increases substantially, raising inter-bit-line coupling noise and compressing sensing margin. To address this, the report inserts a shielding electrode between adjacent bit lines, providing a low-impedance path to ground for coupled signals and cutting off electric-field coupling between bit lines. Tests show that BLS significantly reduces bit-line coupling noise and sensing failures. The conclusion page summarizes the related improvement as “3% → 80%” and states that sensing margin is fully restored. Finally, the report validates a wafer-thinning path for potential POC architectures: backside grinding is applied to the peripheral wafer, while deep n-well engineering provides well isolation. Overall, the report views PUC integration, the retention advantages of floating-body cells, electric-field control through a shared back gate, noise suppression through BLS, and wafer thinning as a mutually complementary technology package. However, further scaling still depends on continuous capacitor improvements and coordinated optimization across multiple device parameters.

Analysis framework

The report first compares the cost, process, and device performance of the 6F² and 4F² approaches, then presents the integration of 4F² vertical-gate DRAM under the PUC architecture. It subsequently validates each key device issue in turn: comparing data-retention performance across different operating modes; using junction engineering to balance leakage, retention, and drive capability; testing the impact of the shared back gate on threshold voltage and adjacent-word-line interference; comparing bit-line noise and sensing performance with and without BLS; and finally validating a wafer-thinning solution based on backside grinding and deep n-well isolation.

Methodology notes

• (Out-of-Vocabulary Method)

  Comparison of 6F² and 4F² Devices and Processes

  The report compares different DRAM cell approaches across dimensions including SAC difficulty, EUV steps, cell efficiency, and device performance to assess the scaling and integration value of the 4F² vertical-gate solution.

• (Out-of-Vocabulary Method)

  Coordinated Trade-Off Among Device Parameters

  Rather than pursuing a single metric in isolation, the report jointly adjusts trap depth, junction depth, and back-gate design to balance data retention against drive current, threshold control against pass-gate suppression, and subthreshold swing against on-current.

• (Out-of-Vocabulary Method)

  Controlled Validation With and Without Bit-Line Shielding

  The report compares bit-line coupling noise, sensing signals, and sensing failures before and after BLS installation to evaluate the actual effectiveness of shielding electrodes in cutting off electric-field coupling between adjacent bit lines.

Key data

• Vertical-Gate Scaling RangeMultiple Generations Beyond 10nmFrom cost and process perspectives, the report concludes that vertical gates can continue scaling for multiple generations.
• SAC Process ChallengeVertical Gate: Free; Buried Gate: ChallengeCost and process comparison between 6F² and 4F².
• EUV StepsVertical Gate: Less; Buried Gate: Ref.The vertical-gate solution requires fewer EUV steps than the reference buried-gate solution.
• Cell EfficiencyVertical Gate: Better; Buried Gate: Ref.Comparison results based on the combination of PUC and Deck.
• Data-Retention Operating ModesStatic Standby, Static Active, Dynamic ModeThe report states that floating-body vertical-gate cells outperform planar DRAM in all three modes.
• BLS-Related Improvement Metric3% → 80%The conclusion page uses this figure to describe the effectiveness of BLS in eliminating major inter-bit-line coupling noise and restoring sensing margin.

Impact & implications

The report believes that 4F² vertical-gate DRAM can use the PUC architecture to improve cell efficiency and extend scaling. Floating-body cells, shared back gates, and BLS respectively improve data retention, threshold and pass-gate interference control, and bit-line sensing reliability. Validation of wafer thinning also provides an integration path for potential POC architectures, giving the overall technology package potential applicability to future high-density DRAM.

Risks

• Trap depth and junction depth require coordinated optimization; otherwise, data retention and drive current could become imbalanced.
• When improving threshold control and pass-gate interference through a shared back gate, trade-offs in subthreshold swing and on-current must be accepted.
• The 4F² structure substantially increases parasitic capacitance between adjacent bit lines; insufficient shielding would compress sensing margin and increase sensing failures.
• Continued vertical-gate scaling still requires ongoing improvements in capacitor technology.

What to watch

• Monitor whether coordinated optimization of trap depth and junction depth can continue to balance data retention and drive current.
• Monitor whether improvements in Vth and pass-gate electric-field interference from the shared back gate can maintain an acceptable Ion and SS trade-off.
• Monitor the effectiveness of BLS in suppressing bit-line coupling noise and sensing failures and preserving sensing margin in subsequent integration.
• Monitor whether the backside-grinding and deep n-well isolation solution can further support potential POC architectures.
• Monitor whether capacitor improvements can support multiple generations of vertical-gate scaling beyond 10nm.