China's AI infrastructure is shifting from a single-chip race to system-level deployment and the token economy

Overview

This report summarizes J.P. Morgan's main observations after a two-day survey at WAIC 2026. The core judgment is that China's AI infrastructure ecosystem has undergone a clear shift: competition is no longer focused only on single-chip benchmarking and capacity expansion, but on system-level deployment, inference commercialization, supernode architecture, and a scalable token economy. The report believes the domestic AI supply chain is entering a volume ramp-up phase, and AI chips, advanced packaging and testing, and fab equipment will all benefit.

Core views

First, the performance threshold for domestic AI chips is rising toward effective Hopper-level, with Iluvatar CoreX's Tiangai 300 claiming a 10%-20% advantage over Hopper architecture on selected inference metrics. Second, PD decoupling has become the recognized mechanism for reducing costs in large-scale LLM inference; inference is seen as the commercially validated application for domestic GPUs, while training is the key scalable market for the next stage. Third, supernodes alleviate insufficient single-chip performance through chip interconnects, switching networks, software, and system-level design, aiming to support trillion-parameter model deployment. Fourth, AI tokens are increasingly viewed as the basis of industrially producible “labor,” and Agentic AI will significantly amplify computing demand.

Analysis framework

The report uses conference research and supply-chain observation to connect and analyze the chips, system architectures, application demand, and beneficiary supply-chain directions showcased at WAIC 2026, and on this basis maps the stock impact to domestic AI chips, back-end packaging and testing, and semiconductor equipment sectors.

Methodology notes

• Supply chain analysisAI infrastructure system-level deployment framework

  Assess supply-chain opportunities from chip performance, system interconnects, inference cost, training scalability, and application token demand.

  The report does not only compare single-chip metrics, but emphasizes that supernodes, liquid cooling, optical interconnects, rack architecture, and software scheduling jointly determine the deployability of next-generation AI infrastructure.

• Investment mappingSupply-chain beneficiary chain

  Map expanding AI computing demand to chip vendors, advanced packaging and testing service providers, and semiconductor equipment manufacturers.

  Based on this, the report recommends Iluvatar CoreX, JCET, NAURA, and AMEC, corresponding respectively to investment opportunities in domestic AI chips, advanced packaging and testing, and fab equipment.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• Iluvatar CoreX-H (9903.HK)

  One of the top picks in the domestic AI chip supply chain, rated OW.

  Strengths

  The report believes it is best positioned among second-tier AI chip makers, with supply assurance and design wins with leading CSP customers.

  Weaknesses

  Domestic AI chips as a whole are still constrained by process nodes and ecosystem maturity.

  Comparison

  Compared with the industry's common limitation of insufficient absolute single-chip performance, Iluvatar CoreX has a relative advantage through Hopper-level inference performance and customer adoption.

  Risks

  Selectivity of inference metrics, training market expansion, supply-chain execution, and ecosystem coordination falling short of expectations.

• JCET-A (600584.SS)

  A beneficiary target in advanced packaging and testing, rated OW.

  Strengths

  Volume ramp-up in AI chips and system-level deployment increase demand for advanced packaging and testing.

  Weaknesses

  Demand realization depends on the shipment pace of domestic AI chips and customer capital expenditure.

  Comparison

  Compared with front-end chip design companies, JCET is more leveraged to the back-end service beneficiary chain.

  Risks

  Advanced packaging demand growing slower than expected, customer concentration, and pricing pressure.

• NAURA-A (002371.SZ)

  A beneficiary target in semiconductor equipment, rated OW.

  Strengths

  The report is positive on memory and advanced logic fab capital expenditure supporting the WFE segment.

  Weaknesses

  Equipment demand is affected by fab expansion cycles and the pace of domestic substitution.

  Comparison

  Like AMEC, it belongs to the report's preferred WFE direction, but the specific beneficiary segments differ.

  Risks

  Slower capital expenditure, longer technology validation cycles, and industry cyclicality.

• AMEC-A (688012.SS)

  A beneficiary target in semiconductor equipment, rated OW.

  Strengths

  Benefits from strong capital expenditure by memory and advanced logic fabs.

  Weaknesses

  It still faces uncertainty in equipment order cycles and the pace of advanced process investment.

  Comparison

  Together with NAURA, it forms the report's preferred combination in the WFE segment.

  Risks

  Fab investment below expectations, slower-than-expected penetration of domestic equipment, and intensified competition.

Key data

• Tiangai 300 inference performance10%-20% higher than Hopper architecture on selected inference metricsThis figure reflects the performance on selected inference metrics claimed by Iluvatar CoreX at launch.
• Kimi K3 model scale example2.8 trillion parametersThe report uses this as an example to illustrate trillion-parameter LLM demand for supernode architecture.
• Supernode scale rangeFrom dozens to thousands of cardsThe report believes the optimal supernode scale across different vertical scenarios is still immature.
• Discussed companies and pricesAMEC-A Rmb342.50; Iluvatar CoreX-H HK$495.20; JCET-A Rmb76.99; NAURA-A Rmb676.91The report notes that unless otherwise stated, prices are as of the close on July 20, 2026; Iluvatar CoreX-H price is as of July 17, 2026.

Impact & implications

The investment implication is that China's AI infrastructure opportunity is expanding from point-specific chip capability to systems engineering and supply-chain coordination. If inference commercialization, training demand, and the token consumption driven by Agentic AI continue to grow, domestic AI chip makers, back-end packaging and testing companies, and semiconductor equipment companies may all benefit. However, the industry still needs to mature further in heterogeneous scheduling standards, token quality measurement, optimal supernode scale, and ecosystem coordination.

Risks

• The absolute single-chip performance of domestic AI chips is still constrained by process nodes.
• The optimal scale of supernode architecture, heterogeneous scheduling standards, and the software ecosystem are not yet mature.
• There is uncertainty around AI token quality measurement, application rollout, and the pace of commercialization.
• Whether the training market can become the next scalable market for domestic GPUs still needs to be validated.
• Demand for semiconductor equipment and advanced packaging depends on fab capital expenditure and the shipment pace of AI chips.

What to watch

• The performance of Iluvatar CoreX Tiangai 300 under real inference workloads and progress in customer validation.
• The actual cost-reduction effect and deployment scope of PD decoupling in large-scale LLM inference.
• The performance of interconnects, liquid cooling, optical interconnects, and software scheduling in supernode solutions ranging from dozens to thousands of cards.
• Whether Agentic AI applications can bring sustained expansion in token demand.
• Transmission of capital expenditure by memory and advanced logic fabs to NAURA, AMEC, and the packaging and testing chain.