Packaging substrate shipments for May rose 36% year-on-year, intensifying competition in advanced packaging

Overview

This is a Nomura update on the semiconductor packaging industry, with core focus on packaging substrate shipments, AI accelerator advanced packaging roadmaps, and the competition between TSMC and Intel in multichip packaging in Japan’s electronics parts sector. The report notes that May packaging substrate shipment value reached a new historical high, with both price and area shipments increasing clearly, indicating stronger demand for high-end packaging.

Core views

The core views of the report are: first, packaging substrate demand has recovered after weakening in April, with May shipment value and average price reaching or near historical highs; second, Rubin-related packaging demand is expected to ramp up in a meaningful way this summer; third, as the technical difficulty rises with larger interposers combined with HBM4, some advanced packaging routes may rely more on 3.5D solutions combining 3D stacking and 2.5D before visibility improves; and fourth, Intel EMIB-T is narrowing the gap with TSMC in high-end AI packaging by strengthening power delivery.

Analysis framework

The report mainly applies industry monthly data tracking, technical paper interpretation, and advanced packaging roadmap comparison: first tracking May Japanese packaging substrate shipment value, area, and unit price; then analyzing the EMIB-T technology paper disclosed by Intel at ECTC to assess packaging power bottlenecks; and finally comparing TSMC and Intel on ecosystem, power delivery, thermal management, CPO, and 3D stacking competitiveness.

Methodology notes

• industry_data_trackingmonthly_shipment_statistics

  Monthly packaging substrate shipment tracking

  Assessing packaging substrate demand strength and high-end product mix changes through shipment value, shipment area, and price per square meter.

• technology_assessmentadvanced_packaging_architecture_comparison

  Comparison of 2.5D, 3.5D, and 3D stacking routes

  The report compares interposer solutions, the EMIB-T silicon bridge solution, and 3D stacking plus 2.5D combined solutions in terms of power, HBM4 integration, and packaging size constraints.

• ecosystem_analysispackaging_ecosystem_competition

  Advanced packaging ecosystem competition

  Evaluating the competitiveness of the TSMC and Intel ecosystems through core capabilities in power delivery, thermal management, CPO, and hybrid bonding.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• Semiconductor packaging substrate supply chain

  Directly benefits from AI accelerator advanced packaging demand and Rubin packaging ramp-up

  Strengths

  Shipment value, area shipment, and average prices all rose in May, indicating improved demand and product mix.

  Weaknesses

  Demand pacing may be affected by AI chip roadmaps, customer ramp timing, and packaging technology transitions.

  Comparison

  High-end packaging substrates are more driven by HBM, multi-die, and larger-form-factor packaging than ordinary PCB.

  Risks

  If Rubin or other AI accelerator mass production is delayed, packaging substrate shipment growth may slow.

• TSMC advanced packaging ecosystem

  Industry competitive benchmark

  Strengths

  Backed by 3DFabric Alliance, it has a strong competitive edge in packaging substrate power delivery and thermal management.

  Weaknesses

  Technical difficulty rises when integrating larger interposers with HBM4, which may affect visibility of future routes.

  Comparison

  Compared with Intel, TSMC’s ecosystem is more mature today, but Intel EMIB-T may catch up after improving power delivery.

  Risks

  If Intel builds a similar ecosystem and gains key customer adoption, TSMC’s competitive edge may be weakened.

• Intel EMIB-T

  Potential competitive intensification factor

  Strengths

  An interposer-less 2.5D packaging solution that improves power delivery through TSV, MIM capacitors, and power mesh layers, supporting four-die and multi-HBM4 integration.

  Weaknesses

  It still needs to complete 2026 ramp preparation and validate customer adoption tempo.

  Comparison

  Different from TSMC’s interposer route, EMIB-T attempts to solve large-package power issues with a silicon bridge approach.

  Risks

  Manufacturing ramp, yields, ecosystem development, and customer adoption may fall short of expectations.

Key data

• May packaging substrate shipment valueabout ¥27.8bn, +36% y/yAbove the previous high of about ¥27.3bn reached in March.
• May packaging substrate area shipment volumeyear-on-year +10%Shows that demand recovery is supported not only by pricing but also by volume.
• May average price per square meterabout ¥1.356mn, year-on-year +23%Higher than April’s prior high of about ¥1.226mn.
• Intel EMIB-T package size120x120mmThe report says this solution can integrate up to 12 HBM4 and is ready for high-volume manufacturing for four-die products at 8x reticle size.
• EMIB-T power improvementpower network voltage drop improvement of 68%-80%Intel says the paper shows stronger in-package power delivery through TSV, power mesh layers, and MIM capacitors.

Impact & implications

For investment implications, synchronized new highs in packaging substrate shipment value and average price support an improving outlook for the AI high-end packaging chain. As Rubin packaging ramps up, related substrate, materials, equipment, and packaging ecosystems may continue to benefit. At the same time, if Intel EMIB-T successfully reaches mass production and is adopted by accelerator customers such as Google, it could change TSMC’s competitive landscape in high-end AI multichip packaging, shifting advanced packaging competition further toward power, thermal, CPO, and 3D stacking capabilities beyond capacity expansion.

Risks

• If the packaging structures of Rubin Ultra or Feynman AI chips change, the rhythm of packaging substrate demand and technology routes may shift.
• The technical difficulty with larger interposer and HBM4 integration may limit progress on some advanced packaging routes.
• Intel EMIB-T still needs to validate ramp production, customer onboarding, and ecosystem-building capabilities.
• Packaging substrate prices and shipments at elevated levels may be vulnerable to AI demand fluctuations, customer buying rhythm, and the broader semiconductor cycle.
• The report does not provide a specific company rating or target price; investment mapping still requires further validation against individual company fundamentals and valuation.

What to watch

• Whether May and subsequent packaging substrate shipment value, area shipment volume, and average price per square meter remain at elevated levels.
• Whether Rubin packaging ramps as expected in the summer, and by around August at the latest.
• Whether Rubin Ultra shifts from a four-die to a dual-die structure, and whether Feynman adopts a dual-module, dual-die 3D stacking configuration.
• Progress on 2026 ramp preparation for Intel EMIB-T four-die, 8x reticle size products.
• Whether accelerator customers such as Google adopt Intel EMIB-T solutions.
• Subsequent partner expansion by TSMC and Intel in ecosystems for power delivery, thermal management, CPO, and 3D stacking.