Nvidia Will Still Dominate 2027 TSMC CoWoS Demand, with Google TPU and AMD CPUs Providing Incremental Upside

Overview

This report centers on the allocation of TSMC and global CoWoS advanced packaging capacity in 2027, with a focus on demand changes from customers such as Nvidia, Broadcom, AMD, MediaTek, AWS/Annapurna, Marvell, and GUC. The report argues that Nvidia’s AI GPU and Vera CPU remain the core drivers of TSMC CoWoS demand, while Google TPU and AMD Venice CPU become important incremental sources in 2027.

Core views

The key judgments are as follows: first, Nvidia may still be the largest TSMC CoWoS user in 2027, with total consumption expected to reach 1.222 million wafers, up 57% YoY; second, Google TPU demand benefits both the Broadcom and MediaTek design-service chains, and MediaTek’s TPU v8t ZebraFish booking volume may be higher than current shipment assumptions; third, CPUs are beginning to consume 2.5D advanced packaging capacity meaningfully, with both Nvidia’s Vera CPU and AMD’s Venice CPU reflecting the expansion of agentic AI server demand; fourth, non-TSMC players such as ASE/SPIL and Amkor will also expand CoWoS-L and CoWoS-R capacity.

Analysis framework

The report combines supply-chain research, customer CoWoS booking decomposition, chip-to-wafer conversion, HBM capacity estimation, and wafer revenue TAM estimation. It first estimates the 2027 CoWoS demand of each AI chip vendor, then derives implied chip shipments, HBM consumption, and advanced-node wafer revenue scale.

Methodology notes

• Supply chain capacity decompositionCoWoS allocation model

  Split CoWoS bookings by customer, packaging type, and foundry/OSAT provider

  The report divides CoWoS demand into CoWoS-L, CoWoS-S, and CoWoS-R, and distinguishes capacity sources such as TSMC, ASE/SPIL, and Amkor to assess the extent to which different customers and supply-chain links benefit.

• Shipment derivationchips per CoWoS wafer conversion

  Derive chip shipments from CoWoS wafer allocations

  Based on the number of chips that can be carried by each CoWoS wafer, the report estimates the implied shipment scale of products such as Nvidia Rubin, Vera CPU, AMD MI series, Venice CPU, Google TPU, and AWS Trainium 3.

• Market sizingHBM and wafer revenue TAM estimate

  Derive HBM demand and wafer revenue TAM from AI chip shipments

  The report further uses assumptions on HBM capacity, HBM die count, process node geometry, chip area, and wafer pricing to estimate 2027 AI HBM demand and the AI wafer revenue market size.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD / US.TSM

  Core CoWoS capacity provider and advanced-node wafer supplier

  Strengths

  Projects such as Nvidia GPU/CPU, Google TPU, AMD GPU, AWS Trainium, and Microsoft Maia all rely on TSMC’s advanced packaging or advanced process capabilities, and the report reiterates OW.

  Weaknesses

  Capacity expansion requires continued capital spending, and some incremental demand may be diverted to non-TSMC players.

  Comparison

  Compared with ASE/SPIL and Amkor, TSMC remains at the core of CoWoS capacity and advanced processes.

  Risks

  CoWoS expansion slower than expected, changes in customer demand, advanced-process yield issues, or geopolitical and export-control risks.

• Nvidia

  Largest CoWoS demand source

  Strengths

  Rubin, Blackwell, Rubin Ultra, and Vera CPU drive 2027 CoWoS consumption to 1.222 million wafers, continuing to dominate TSMC CoWoS demand.

  Weaknesses

  Highly dependent on the advanced packaging and HBM supply chain.

  Comparison

  Nvidia’s 2027 CoWoS demand accounts for about 45%, still significantly above Broadcom and AMD.

  Risks

  Slower AI server demand, substitute chip competition, or packaging/HBM supply bottlenecks.

• MediaTek

  Beneficiary of Google TPU design services

  Strengths

  TPU v8t ZebraFish corresponds to 180k CoWoS-S wafers of bookings, implying about 3.6 million TPUs, and the report names it a Top Pick.

  Weaknesses

  The report’s current shipment assumption is constrained by potential ABF substrate shortages.

  Comparison

  A beneficiary of the Google TPU ecosystem alongside Broadcom, but MediaTek’s orders are more directly tied to TPU v8t ZebraFish.

  Risks

  Insufficient ABF substrate supply, shifts in the Google TPU project timeline, and competition with design-service partners such as Broadcom.

• Broadcom

  Demand source for Google TPU and Meta MTIA-related CoWoS

  Strengths

  Total 2027 CoWoS consumption is expected to rise to 484k wafers, with Google TPU v7/v8i and Meta MTIAv3 providing the main demand.

  Weaknesses

  Demand is split across multiple ASIC projects, so changes in the timing of any single project can affect allocation.

  Comparison

  2027 CoWoS demand is second only to Nvidia and above MediaTek.

  Risks

  Cloud providers’ ASIC in-house development pace, Google TPU generation transitions, and uncertainty around packaging-capacity allocation.

• ADVANCED MICRO DEVICES INC / US.AMD

  Customer driving CoWoS demand growth through GPU and Venice CPU

  Strengths

  2027 CoWoS consumption is expected to grow 308% YoY to 530k wafers, and Venice CPU implies about 6.75 million units shipped.

  Weaknesses

  GPU and CPU production is split between TSMC and non-TSMC camps, making supply-chain execution more complex.

  Comparison

  The growth rate is higher than Nvidia’s and Broadcom’s, but absolute CoWoS demand remains below Nvidia’s.

  Risks

  MI-series GPU competitiveness, the pace of Venice CPU ramp-up, and the availability of 2nm and advanced packaging capacity.

• ASE/SPIL and Amkor

  Beneficiaries of non-TSMC advanced packaging expansion

  Strengths

  The report expects non-TSMC players’ CoWoS capacity to expand to 80k wafers per month by end-2027, focusing on CoWoS-L and CoWoS-R.

  Weaknesses

  Compared with TSMC, the advanced packaging ecosystem and customer lock-in may be weaker.

  Comparison

  ASE/SPIL’s FoCoS+CoWoS capacity is expected to rise from 30k wpm at end-2026 to 50k wpm at end-2027, while Amkor’s rises from 20k wpm to 30k wpm.

  Risks

  Customer qualification progress, yield ramp-up, and competitive pressure from TSMC expansion.

Key data

• 2027 Global CoWoS total demand2,694k wafersThe exhibit table shows total demand rising from 1,394k in 2026e to 2,694k in 2027e, up 93% YoY.
• Nvidia 2027 CoWoS consumption1,222k wafersUp 57% YoY, of which TSMC CoWoS-L is about 910k and CoWoS-R for Vera CPU is about 130k.
• AMD 2027 CoWoS consumption530k wafersUp 308% YoY; Venice CPU CoWoS bookings rise from 50k in 2026 to 270k in 2027.
• Broadcom 2027 CoWoS consumption484k wafersUp 61% YoY; Google TPU Ironwood and SunFish together account for 343k CoWoS-S bookings.
• MediaTek 2027 CoWoS consumption180k wafersMainly for Google TPU v8t ZebraFish, implying about 3.6 million TPUs.
• 2027 AI HBM demand50,609mn GbThe exhibit table shows 2027 AI HBM demand of about 50,609 million Gb.
• 2027 AI wafer revenue TAMUS$46,418mnThe exhibit table estimates AI wafer revenue TAM at about US$46.418 billion, and the main text summarizes it as at least US$47 billion.
• TSMC AI-related revenue CAGR60%The exhibit title suggests TSMC’s AI-related revenue CAGR from 2024 to 2029e could reach 60%.

Impact & implications

In investment terms, advanced packaging is shifting from an AI GPU bottleneck into a key resource contested by GPUs, CPUs, and ASICs. Nvidia remains the largest source of demand, but Google TPU, AMD Venice CPU, AWS Trainium, Microsoft Maia, and Meta MTIA ASIC/CPU projects expand the demand base, benefiting TSMC, ASE/SPIL, Amkor, and other packaging capacity providers, as well as MediaTek, Broadcom, Alchip, GUC, and other AI ASIC design-service chains. The report is broadly positive on Taiwan’s AI semiconductor supply chain, with particular emphasis on MediaTek’s upside in Google TPU.

Risks

• CoWoS capacity expansion or yield ramp-up may fall short of expectations, preventing 2027 customer allocations from being realized.
• ABF substrates, T-Glass, HBM, or advanced-node wafer supply may be insufficient, limiting actual TPU, GPU, and CPU shipments.
• AI cloud capex or inference demand may come in below expectations, weakening advanced packaging demand from Nvidia, Google, AMD, AWS, and others.
• U.S. executive orders, export controls, and geopolitical restrictions may affect related securities trading, supply-chain shipments, and customer orders.
• The 2027e figures in the report rely heavily on supply-chain research and booking assumptions; if customer roadmaps or foundry/OSAT allocation changes, the estimates may deviate.

What to watch

• Whether TSMC’s CoWoS capacity reaches the assumed 200k wafers/month by end-2027.
• The production ramp of Nvidia Rubin, Rubin Ultra, and Vera CPU, and actual CoWoS-L/CoWoS-R consumption.
• Whether MediaTek can secure more T-Glass and ABF substrate supply for Google TPU v8t, allowing shipment assumptions to be revised upward.
• The extent to which AMD Venice CPU shipments rise from about 1.25 million in 2026 to about 6.75 million in 2027.
• Changes in share between Broadcom’s TPU v8i SunFish and MediaTek’s TPU v8t ZebraFish in the Google TPU ecosystem.
• Qualification and capacity expansion progress for CoWoS-L and CoWoS-R among non-TSMC players such as ASE/SPIL and Amkor.
• Whether 2027 AI HBM demand approaches 50,609mn Gb, and the supply capabilities of HBM vendors Hynix, Micron, and Samsung.