CoWoS-L and SoIC remain the key variables in the Asia-Pacific AI chip supply chain
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CoWoS-L and SoIC remain the key variables in the Asia-Pacific AI chip supply chain
Morgan Stanley believes that the key questions around NVIDIA Rubin Ultra, Google 2nm TPU, and the evolution of LPU/HBM ultimately come down to whether TSMC CoWoS-L, SoIC, and 3nm capacity can support larger chip designs at reasonable cost.
- TSMC CoWoS-L is viewed as an important packaging solution for NVIDIA Rubin Ultra's four-die packaging and Google's 2nm TPU, but interposer warpage and other technical issues still need to be resolved.
- Whether Rubin Ultra uses two dies or four dies has little impact on NVIDIA's consumption of TSMC wafer capacity or on ASE/KYEC packaging and test assumptions; the main differences are thermal design and rack-scale CPO adoption.
- The report maintains a positive view on MediaTek's 3nm TPU ZebraFish, expecting the 2026 assumption of 400,000 units and about US$1.6bn in revenue to be achievable, and reiterating the 2027 assumption of 2.5 million units and about US$10bn in revenue.
- TSMC's SoIC capacity expansion expectations were revised up; the report says 2027 capacity was raised from 28kwpm to 45kwpm and further to 78kwpm in 2028, though equipment qualification cycles may affect the conversion to actual output.
- The report believes that at least through 2027, power is not the main constraint on TSMC AI chip demand; more attention should be paid to CoWoS, SoIC, ABF substrates, and front-end 2/3nm wafer supply.
Report interpretation
Overview
This report addresses five investor questions about the Asia-Pacific AI semiconductor supply chain, focusing on NVIDIA Rubin Ultra packaging form factors, beneficiaries of NVIDIA LPU foundry demand, whether Samsung's future HBM base dies will shift to TSMC 3nm, the impact of Broadcom's cooperation with Google on MediaTek's TPU opportunity, and what incremental compute and power capacity imply for chip demand. The core conclusion is that large AI GPUs/ASICs are shifting the competitive focus toward supply-chain bottlenecks such as CoWoS-L, SoIC, 3nm process technology, HBM base dies, and ABF substrates.
Core views
The report argues that TSMC CoWoS-L remains the preferred advanced packaging solution for large AI chips, with better performance and reliability than Intel EMIB-T, although TSMC still needs to solve interposer warpage and related issues. NVIDIA Rubin Ultra's eventual two-die or four-die packaging has limited impact on assumptions for TSMC wafer consumption and ASE/KYEC OSAT volumes. Google's 2nm TPU HumuFish is still being evaluated for TSMC CoWoS-L, Intel EMIB-T, or a dual-sourcing approach. MediaTek's 3nm TPU ZebraFish has slightly higher power consumption and is undergoing some metal-layer ECO work, but the report does not see this as affecting the 2H26 mass-production timeline.
Analysis framework
The report uses supply-chain research, customer project milestone tracking, advanced packaging capacity estimation, power-to-GW chip volume conversion, and revenue exposure and valuation comparisons among AI semiconductor companies to answer investor concerns. The analysis focuses not on a single chip specification, but on the capacity alignment among chip design, foundry, advanced packaging, testing, substrates, and memory base dies.
Methodology notes
Use packaging and testing, equipment, foundry, and substrate supply-chain information to validate project mass-production pace and capacity expansion.
The report repeatedly uses 'checks' as evidence, for example that MediaTek's 3nm TPU is on track for 2H26 mass production, TSMC's SoIC capacity was revised up, and TSMC is preparing 4/5nm to 3nm capacity for AI demand.
Compare the performance, reliability, cost, and technical risks of large multi-reticle chips using TSMC CoWoS-L versus Intel EMIB-T.
The report concludes that CoWoS is superior in performance and reliability, but TSMC still needs to resolve interposer warpage; if large-reticle chip issues cannot be solved, Intel EMIB-T could gain share in Google 2nm TPU and other ASIC projects.
Use monthly capacity, annual output, project lifecycle demand, and GW compute announcements to derive CoWoS, SoIC, and front-end 2/3nm wafer demand.
The report estimates total lifecycle TSMC CoWoS demand for the relevant projects at 953k wafers and front-end 2/3nm wafer demand at 652k wafers, and concludes that the 2027 TSMC annual CoWoS demand of 259k wafers for these projects is achievable.
Asset mapping & comparison
Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).
- TSMCThe core foundry and advanced packaging supplier for AI GPUs/ASICs, covering CoWoS-L, SoIC, 3nm HBM base dies, and front-end 2/3nm wafers.
- Strengths
- The CoWoS roadmap already shows support for nine reticles in 2027; performance and reliability are better than EMIB-T; SoIC capacity expectations were raised, and AI memory and HBM base dies could become growth drivers after 2028.
- Weaknesses
- CoWoS-L still needs to solve interposer warpage and other technical issues; SoIC equipment qualification takes longer, slowing the conversion from capacity to actual output.
- Comparison
- Compared with Intel EMIB-T, CoWoS offers stronger performance and reliability; if TSMC does not solve its technical issues, Intel could gain share in Google TPU or other ASIC projects.
- Risks
- Large-chip packaging yield, cost, warpage, ABF substrate constraints, and slower-than-expected capacity ramp-up.
- MediaTekAn important participant in Google's 3nm TPU ZebraFish ASIC opportunity.
- Strengths
- The report believes the 2H26 mass-production schedule is not delayed, and the assumptions of 400,000 units in 2026 and 2.5 million units in 2027 are still reiterated; the outlook for ABF substrate supply is improving.
- Weaknesses
- The chip is undergoing some metal-layer ECO work because power consumption is slightly higher, and the market has questions about its strategic position in the TPU supply chain.
- Comparison
- Broadcom's cooperation with Google has raised concerns about MediaTek's opportunity, but the report believes this does not change its positive view on MediaTek's 3nm TPU.
- Risks
- Post-ECO performance and quality, Google's validation progress, ABF supply, customer order allocation, and changes in the competitive landscape.
- NVIDIARubin Ultra GPU, LPU, and future Feynman GPU programs drive demand for CoWoS, SoIC, testing, and wafers.
- Strengths
- Rubin Ultra is part of the 2027 roadmap, LPU targets low-latency AI inference, and future GPUs may require 1-2GB SRAM stacking, creating SoIC demand.
- Weaknesses
- The two-die versus four-die Rubin Ultra design has not yet been finalized, and thermal design and CPO adoption may differ.
- Comparison
- Whether two-die or four-die, the report believes the impact on TSMC wafer demand and ASE/KYEC packaging and test consumption assumptions is limited.
- Risks
- Packaging form factor, thermal design, CPO adoption, supply-chain capacity, and realization of low-latency inference demand.
- SamsungCurrent LP30 LPU uses Samsung 7nm, future LP35 may be dual-sourced with TSMC; Samsung HBM base dies may also shift to TSMC 3nm in the future.
- Strengths
- It already has a position in existing LPU foundry work, and the report also includes Samsung in the Asia semiconductor OW list.
- Weaknesses
- HBM4e/HBM5 base dies require substantial customization and IP support, and the report sees TSMC 3nm as becoming an important global node.
- Comparison
- TSMC may gain more opportunities in AI memory and base dies through 3nm and advanced packaging.
- Risks
- Advanced-node competition, customer dual-sourcing strategies, and changes in the outsourcing path for HBM base dies.
- ASE / KYECImportant participants in packaging and testing assumptions for NVIDIA and the AI supply chain.
- Strengths
- Changes in Rubin Ultra packaging form factor have little impact on ASE/KYEC packaging and test assumptions, and the report is OW on KYEC and ASE among Asia semiconductor names.
- Weaknesses
- Growth depends on AI chip packaging and testing demand and on the pace of advanced packaging.
- Comparison
- Compared with the foundry segment, packaging and testing benefits are more tied to utilization and AI semiconductor revenue exposure.
- Risks
- Customer project delays, packaging and testing capacity allocation, and a shift in advanced packaging bottlenecks.
- Alchip / GUC / FOCI / HimaxBeneficiaries in ASIC design services and the CPO supply chain.
- Strengths
- The report explicitly states a positive view on Asian ASIC design service providers Alchip and GUC, as well as CPO suppliers FOCI and Himax.
- Weaknesses
- Some demand is still at the design, pilot production, or customer onboarding stage.
- Comparison
- Compared with foundries and OSATs, the benefit depends more on the landing of customer ASIC projects and the pace of CPO adoption.
- Risks
- ASIC project cancellations, customer concentration, slower-than-expected CPO adoption, and intensifying competition.
Key data
- MediaTek 3nm TPU 2026 assumption400k units / US$1.6bn revenueThe report believes ZebraFish will reach mass production in 2H26 on schedule, making this 2026 assumption achievable.
- MediaTek 3nm TPU 2027 assumption2.5mn units / US$10bn revenueThe report reiterates this higher 2027 revenue assumption as ABF substrate supply improves.
- TSMC SoIC year-end capacity outlook2026e 14kwpm；2027e 45kwpm；2028e 78kwpmThe report says 2027e SoIC capacity expectations were raised from 28kwpm to 45kwpm, and to 78kwpm in 2028e.
- TSMC SoIC production outlook2026e 10kwpm；2027e 30kwpm；2028e 60kwpmEquipment qualification takes longer than CoWoS, at roughly six months or more, so the conversion from capacity to output is lower.
- TSMC CoWoS total year-end 2027 capacity target160-170kwpmBased on this, the report believes the 2027 annual CoWoS demand of 259k wafers from related projects is achievable.
- Total lifecycle demand for related projectsCoWoS 953k wafers；front-end 2/3nm 652k wafersEstimated based on compute deployment projects from OpenAI, NVIDIA, AMD, and Google/Broadcom, among others.
- NVIDIA LPU roadmapLP30 Samsung 7nm；LP35 2027 or dual-sourced from TSMC/Samsung；LP40 2028 or TSMC 3nm and SoICThe report believes that, driven by low-latency inference demand, LPU may create additional opportunities for TSMC advanced nodes and SoIC in the future.
- New compute-deal examplesOpenAI-AWS Trainium 2GW；Google TPU 3.5GW；Google/Broadcom 2.5GWThe report uses a GW-to-chip-volume conversion framework to discuss what power capacity means for chip demand.
Impact & implications
For investors, the report extends the beneficiaries of AI compute expansion from pure GPU demand to advanced packaging, SoIC, HBM base dies, packaging and testing, substrates, and ASIC design services. TSMC is one of the most important structural beneficiaries, while MediaTek's Google TPU-related opportunity remains attractive; ASE, KYEC, Samsung, Aspeed, as well as Alchip, GUC, FOCI, and Himax are also viewed positively or as beneficiaries. The main disagreements remain the Google 2nm TPU packaging choice, progress in resolving TSMC CoWoS-L technical issues, ABF supply, and SoIC ramp-up.
Risks
- If TSMC CoWoS-L cannot solve interposer warpage and other technical issues for large-reticle chips, Intel EMIB-T could gain share in Google 2nm TPU or other ASIC projects.
- Although MediaTek's 3nm TPU is not expected to be delayed in mass production, slightly higher power consumption and ECO work may still create risks around validation, yield, or customer acceptance.
- SoIC equipment qualification cycles are long, which may lead to a large gap between nominal capacity and actual output.
- Constraints in any one of ABF substrates, HBM base dies, front-end 2/3nm wafers, or advanced packaging could affect AI chip shipment schedules.
- The report involves business relationships and potential conflicts of interest between Morgan Stanley and several covered companies; investors should treat this research as only one input to their decision-making.
- Export controls, U.S. executive orders, and related compliance restrictions may affect investment and trading activity in certain securities or entities.
What to watch
- Whether NVIDIA Rubin Ultra ultimately adopts a two-die or four-die package, and any corresponding changes in thermal design and CPO adoption.
- Whether Google's 2nm TPU HumuFish ultimately uses TSMC CoWoS-L, Intel EMIB-T, or a dual-sourcing approach.
- Progress on the cost, yield, reliability, and interposer warpage issues in TSMC's nine-reticle CoWoS-L solution.
- Completion of ECO work for MediaTek's 3nm TPU ZebraFish, Google's validation progress, 2H26 mass production, and 2027 ABF substrate supply.
- TSMC SoIC expansion progress in Miaoli, Chiayi AP7, and Arizona, and the actual output conversion during 2026-2028.
- The speed of TSMC 3nm adoption in HBM4e/HBM5 base dies, especially the customized needs of Korean HBM vendors.
- Whether the GW compute projects related to OpenAI, AWS, Google, Broadcom, NVIDIA, and AMD are launched according to announced plans.