Huawei's Tau Scaling Technology Drives Chip Performance Improvement
AI summary card
Huawei's Tau Scaling Technology Drives Chip Performance Improvement
Huawei proposes the Tau scaling concept, leveraging innovations such as 3D integration to enhance chip performance, potentially boosting demand for advanced packaging equipment.
- Huawei introduces the Tau scaling concept, emphasizing latency reduction over geometric scaling
- LogicFolding enables vertical stacking of logic, analog, and memory layers
- Kirin 2026 achieves a 55% increase in transistor density, reaching 238 MTr/mm²
- Targets equivalent 1.4nm logic density by 2031
- Positive outlook for advanced packaging equipment and service providers
Report interpretation
Overview
This report analyzes Huawei’s newly proposed Tau (τ) scaling law presented at the IEEE ISCAS conference—a novel chip scaling philosophy focusing on latency reduction rather than transistor miniaturization. The approach enhances performance through 3D integration, hybrid bonding, and logic/memory co-integration, offering significant value under constraints of advanced process nodes. The report highlights that this technology could stimulate growth across the advanced packaging equipment and related supply chain segments.
Core views
Huawei’s new Tau scaling concept addresses challenges posed by limitations in advanced process nodes, leveraging technologies like 3D integration and hybrid bonding to boost chip performance. Under the LogicFolding architecture, the Kirin 2026 chip achieves a 55% increase in transistor density, reaching 238 MTr/mm², with projections exceeding 400 MTr/mm² in the future. Despite geometric scaling constraints, this design innovation demonstrates comprehensive optimization capabilities across chip, circuit, and system levels. The report suggests this shift may catalyze industry-wide transformation toward chip design innovation, benefiting advanced packaging equipment suppliers, OSATs, foundries, and EDA tool vendors. Key data points include Huawei’s claim that the Kirin 2026 chip improves power efficiency by 41% at a fixed device node and targets an equivalent 1.4nm logic density by 2031. The report also notes emerging challenges such as thermal constraints and EDA limitations. On the roadmap, Huawei plans to launch a series of LogicFolding-based chips from 2026 to 2029, with progressively increasing frequencies, illustrating its clear technical evolution path.
Analysis framework
The institution first introduces Huawei’s Tau scaling concept, which uses latency reduction as the performance metric instead of traditional geometric scaling. It then illustrates the implementation through the LogicFolding case study—vertically stacking logic, analog, and memory circuits using 1.5μm hybrid bonding. Analysis proceeds across three dimensions: performance gains, technical constraints, and industry implications. First, it emphasizes improvements in transistor density and power efficiency; second, it acknowledges continued limitations in geometric scaling due to lack of EUV lithography tools; third, it posits that this approach may drive broader industry innovation in chip design. The analytical logic flows coherently from technical principles to real-world applications and then to sector-wide impacts.
Methodology notes
Supply-Demand Framework
Analyzes how technological innovations (e.g., Huawei’s Tau scaling) alter supply-side dynamics and align with market demand to forecast industry trends.
Upstream-Midstream-Downstream Industry Chain Transmission
Examines how new technologies (e.g., Tau scaling) propagate from design through manufacturing, packaging, and equipment segments, affecting all participants in the value chain.
Free Cash Flow Analysis
Evaluates a company’s future cash flow generation to support valuation and investment decisions, such as setting target prices based on expected revenue and earnings recovery.
Asset mapping & comparison
Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).
- ASMPT (0522.HK)Benefits from advanced packaging equipment and system design innovation
- Strengths
- Offers a broad portfolio of advanced packaging solutions
- Weaknesses
- Faces risks from market competition and export controls
- Comparison
- Holds a leading position in advanced packaging
- Risks
- Intensifying industry competition, slowdown in AI infrastructure investment
Key data
- Kirin 2026 Chip Transistor Density238 MTr/mm²55% improvement over previous generation
- Kirin 2026 Chip Power Efficiency Improvement41%At fixed device node
- Target Logic Density by 2031Equivalent to 1.4nmAchieved via Tau scaling technology
- ASMPT Target PriceHK$180Based on peak 2027E P/E of 37x
Impact & implications
This technology signals a strategic shift in chip design—from reliance on geometric scaling toward holistic performance optimization—creating structural industry impacts. The report identifies advanced packaging equipment providers, OSATs, foundries, and EDA tool vendors as primary beneficiaries. Against the backdrop of AI-driven growth in advanced packaging orders, companies like ASMPT are well-positioned to leverage their solutions for competitive advantage and potential valuation re-rating. Moreover, this approach offers a viable pathway for China’s semiconductor ecosystem to navigate external constraints.
Risks
- Slowing AI infrastructure investment leading to reduced demand
- Loss of TCB market share
- Disruption from alternative technologies (e.g., hybrid bonding)
- Intensifying industry competition
- Expansion of backend equipment export restrictions
What to watch
- Progress of Huawei’s future chip products
- Growth in advanced packaging orders
- Changes in ASMPT’s market share and profitability