TSMC's technology roadmap reinforces leadership in advanced process technologies and AI packaging

Overview

This report is JPMorgan's quick-take commentary on TSMC's 2026 North America Technology Symposium, focusing on TSMC's roadmap in advanced logic processes, advanced packaging, 3D stacking, silicon photonics, and high-voltage DDIC processes. The report takes an overall positive stance, believing these technology nodes continue to demonstrate TSMC's leadership in AI, HPC, and mobile applications, and support its over 95% market share and high barriers to entry in advanced applications.

Core views

The core view of the report is that TSMC's structural growth momentum remains strong. A13, A14, A12, and N2U show that the advanced process platform continues to progress on an annual product cadence; CoWoS expands to 14x reticle size and beyond, addressing AI chip demand for larger packaging and more HBM integration; SoIC and COUPE enhance 3D stacking and optical interconnect capabilities. JPMorgan believes tight supply in advanced nodes such as N4, N3, and N2 may continue through 2027 and even early 2028, and together with high utilization and ASP improvement, this sets up TSMC shares favorably over the next few quarters.

Analysis framework

Using disclosures from the technology symposium as the main thread, the report combines TSMC's new processes, new packaging technologies, and product timelines with AI/HPC customer demand, capacity expansion, supply chain impact, and valuation framework. The analysis focuses on process performance metrics, mass production timing, relative positioning versus competing technologies, potential positive and negative implications for supply chain companies, and the forward P/E assumption implied by the target price.

Methodology notes

• Valuation methods12-month forward P/E

  The target price is based on about 20x 12-month forward P/E.

  JPMorgan sets its Dec-26 target price of NT$2500 based on about 20x 12-month forward P/E, justified by margin improvement and slightly faster growth; this target multiple is above TSMC's five-year historical average.

• Technology roadmapAdvanced process node tracking

  Assess technology leadership through the performance, compatibility, and mass production timing of nodes such as A13, A14, A12, and N2U.

  The report uses process area, speed, power consumption, logic density, backside power delivery, and the adoption pace of High-NA EUV as important bases for evaluating TSMC's technology moat and customers' migration capability.

• Supply chain impactAdvanced packaging capacity and alternative technology comparison

  Use CoWoS expansion, SoIC adoption, and CoPoS progress to judge which parts of the AI packaging supply chain may benefit or face pressure.

  The report believes that larger CoWoS package sizes may weaken the relative advantage of Intel's EMIB supply chain, while the lack of mention of CoPoS is slightly negative for the PLP supply chain; progress in SoIC is positive for related equipment suppliers.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• TSMC (2330.TW)

  Report subject and core recommended name

  Strengths

  Clear roadmap for advanced process technologies, strong AI/HPC demand, continued progress in advanced packaging and interconnect technologies such as CoWoS, SoIC, and COUPE, and over 95% market share in advanced applications.

  Weaknesses

  Capital expenditure and advanced capacity build-out have long cycles, and part of demand is still affected by PC/smartphone cycles.

  Comparison

  Compared with followers, TSMC has a leading advantage in technology and manufacturing execution, with customer design and mass production ramp windows of about 3-5 years.

  Risks

  Debate over the sustainability of the AI capital expenditure cycle, as well as weak PC/smartphone demand in 2H26.

• Grand Process Technology (3131.TW)

  Potential beneficiary in the SoIC supply chain

  Strengths

  The report believes major AI chips will adopt SoIC more broadly in 2028 and beyond, potentially benefiting related equipment suppliers.

  Weaknesses

  The pace of benefit realization depends on actual SoIC mass production and customer adoption progress.

  Comparison

  Compared with other advanced packaging equipment chain companies, its benefits are more concentrated on SoIC advancement.

  Risks

  AI chip adoption pace falls short of expectations or TSMC capacity expansion is delayed.

• Scientech (3583.TW)

  Potential beneficiary in the SoIC supply chain

  Strengths

  The report explicitly states that SoIC commentary should be favorable for equipment suppliers such as Scientech.

  Weaknesses

  Order and revenue realization still depend on SoIC engineering and mass production milestones.

  Comparison

  Its benefit logic is similar to GPTC, coming from increased adoption of 3D stacking in AI chips.

  Risks

  SoIC adoption falls short of expectations or the AI packaging investment cycle fluctuates.

• UMC (2303.TW)

  Potentially negatively affected by N16HV

  Strengths

  Currently an important foundry supplier for iPhone OLED DDIC using 22/28nm HV processes.

  Weaknesses

  If Apple DDIC migrates to TSMC's N16 FinFET platform, UMC's related wafer production share may come under pressure.

  Comparison

  TSMC N16HV offers clear improvements over N28HV in density and power consumption, which may enhance the attractiveness of the FinFET platform.

  Risks

  Uncertainty over the decision, timeline, and customer adoption for iPhone DDIC migration.

Key data

• RatingOverweightThe report maintains an Overweight rating on TSMC.
• Current share priceNT$2050.0Price as of April 22, 2026.
• Target priceNT$2500.0Dec-26 target price.
• Implied upside21.95%Calculated based on the NT$2500 target price and NT$2050 current price.
• A13 mass production timing2029A13 is a direct shrink of A14, with a 6% area improvement and backward-compatible design rules.
• N2U mass production timing2028Versus N2P, it can deliver a 3%-4% speed gain or 8%-10% power reduction, with a 1.02-1.03x increase in logic density.
• CoWoS capacity forecastYE26 about 115k wfpm; YE27 about 155k wfpmEquivalent to about 69% YoY and about 35% YoY growth, respectively.
• CoWoS package size roadmap14x reticle size in 2028; above 14x reticle size in 202914x reticle size can integrate about 10 large compute dies and 20 HBM stacks.
• SoIC performance improvementA14-to-A14 SoIC has 1.8x higher die-to-die I/O density than N2-on-N2 SoICExpected to be used in production in 2029.
• COUPE Gen 2Mass production in 2H26Versus board-level pluggable solutions, it offers 2x efficiency improvement and 10x lower latency.
• N16HVAvailable in 2026Versus N28HV, it improves smartphone DDIC gate density by 41% and reduces power consumption by 35%.

Impact & implications

For TSMC, the technology roadmap reinforces its leadership in AI/HPC advanced process technologies and packaging, and could support higher capital expenditure targets, upward revisions to 2026 revenue guidance, and better-than-expected gross margin. For the supply chain, progress in SoIC is positive for equipment suppliers such as GPTC and Scientech; larger CoWoS package sizes may weaken the differentiated appeal of Intel's EMIB supply chain; the lack of mention of CoPoS is slightly negative for the PLP supply chain; and if N16HV is adopted for Apple DDIC, it could reshape the shares of Novatek and LX Semicon in iPhone DDIC and pressure UMC, which currently uses 22/28nm HV processes.

Risks

• There is debate over the duration of the AI capital expenditure growth cycle.
• Weak PC and smartphone demand in 2H26 could pose downside risk to the rating and target price.
• The build-out cycle for advanced process and advanced packaging capacity is long, and delays in mass production or customer qualification could affect growth realization.
• Industry supply tightness may create competitive noise, and the technology and manufacturing milestones of followers still need to be monitored.
• CoPoS is still in the engineering stage, and initial adoption depends on whether engineering milestones can be achieved.

What to watch

• Customer migration speed and mass production progress for A13, A14, A12, and N2U.
• Whether High-NA EUV adoption is delayed to around the A10 node as the report expects.
• Whether CoWoS capacity expands as planned to about 115k wfpm by YE26 and about 155k wfpm by YE27.
• Execution progress for 14x reticle size CoWoS in 2028, larger CoWoS in 2029, and 40-reticle SoW-X.
• Adoption of SoIC in AI chips such as NVIDIA Feynman GPUs, Google TPU v9, and Amazon Trainium 4.
• Mass production of COUPE Gen 2 in 2H26 and customer adoption progress related to CPO.
• Whether Apple decides before 2H26 to migrate iPhone DDIC to the 16nm FinFET platform.
• Whether TSMC's long-term capital expenditure target, 2026 revenue guidance, and gross margin are revised upward or exceed expectations.