Rubin Ultra May Adopt Tiered HBM Configurations, While AI Compute Expansion Continues to Drive Demand for CoWoS, Wafers, Testing, and Optical Interconnects

Overview

The report focuses on architectural adjustments, memory configurations, server racks, optical interconnects, advanced packaging, testing demand, and power constraints in the AI GPU and ASIC supply chain. The core view is that Rubin Ultra may alleviate memory shortages and cost pressures through tiered HBM specifications; Kyber racks face delays due to PCB and cooling issues, and NVIDIA may extend Oberon NVL72 in the near term while using CPO/NPO to support larger-scale interconnects. At the same time, the expansion of Google TPU and CPU, the Rubin series, and other custom ASICs will continue to drive demand for CoWoS, advanced-node wafers, HBM, and testing.

Core views

First, Rubin Ultra may form multiple HBM configuration tiers, with high-end products using HBM4e and lower-end products using HBM4, to adapt to different workloads and alleviate supply and cost pressures. Second, lowering memory specifications may weaken decoding performance for long-context large models, but reduced memory per chip may also increase total accelerator shipments. Third, there is still no clear delivery timeline for Kyber racks, and first-generation Rubin Ultra systems may continue to use the Oberon NVL72 architecture and achieve NVL576-level connectivity through CPO/NPO. Fourth, due to foundry process and SerDes speed limitations, Chinese AI GPU vendors are more inclined to use NPO to build supernodes, while NVIDIA's CPO path may create differentiation in scale-out expansion. Fifth, demand for Google TPU, CPU, and Rubin supports continued growth in the AI semiconductor supply chain from 2026 to 2027, but power supply may become a stricter constraint than chip capacity.

Analysis framework

The report combines supply-chain channel checks with bottom-up estimates: estimating accelerator shipments and memory demand based on CoWoS wafer allocation, chips per wafer, and HBM configurations; estimating wafer revenue opportunities based on process nodes, chiplet counts, wafer consumption, and wafer prices; incorporating HGX servers into the chip-and-rack matching model by treating nine units as equivalent to one NVL72 rack; and estimating overall power capacity requirements using average power consumption per GPU or ASIC.

Methodology notes

• Supply chain researchChannel checks

  Assess product specifications and delivery cadence through feedback from the memory, packaging, server, and testing industry chains.

  Channel feedback is used to evaluate Rubin Ultra's tiered HBM plan, Kyber rack delays, CPO/NPO adoption direction, and Google TPU and CPU testing demand.

• Capacity and shipment estimationCoWoS bottom-up model

  Use CoWoS wafer allocation and the number of chips producible per wafer to estimate accelerator shipments.

  The model further combines HBM capacity, stack count, and generation per chip to estimate total HBM demand, and breaks down CoWoS demand by customer and chip vendor.

• System shipment matchingChip-to-rack equivalence conversion

  Convert HGX systems and NVL72 racks into a unified GPU consumption metric.

  The report assumes that nine HGX servers, each containing eight GPUs, are equivalent to one NVL72 rack, and uses this to rematch Blackwell chip supply with server rack demand.

• Infrastructure constraintsPower capacity conversion

  Estimate required power capacity by multiplying the number of accelerators by average thermal design power.

  Using an illustrative parameter of approximately 2 kW per GPU or ASIC, the report converts around 19 million accelerators in 2027 into about 38 GW of power demand to test whether chip demand forecasts can be supported by infrastructure.

Asset mapping & comparison

Structured mapping from thesis to named assets (strengths, weaknesses, peers, risks).

• NVIDIA

  Core driver of Rubin, Rubin Ultra, Blackwell, and supernode architectures

  Strengths

  Has a complete ecosystem from GPUs and NVLink to rack-level systems; the CPO roadmap is expected to strengthen large-scale interconnect performance, and the Rubin series is expected to enter a volume ramp cycle in the second half of 2026.

  Weaknesses

  Rubin Ultra faces trade-offs between HBM supply and cost, while Kyber racks have uncertainties around PCB, cooling, and delivery timing.

  Comparison

  Compared with Chinese supernode solutions using NPO, NVIDIA is more inclined to use CPO to improve cross-rack scale-out performance.

  Risks

  HBM specification adjustments affecting performance, rack delays, insufficient power, supply-chain buffer inventory digestion below expectations, and regulatory restrictions.

• TSMC

  Key provider of advanced-node wafers and CoWoS packaging capacity for AI GPUs and ASICs

  Strengths

  Benefits from synchronous growth in GPUs, TPUs, and custom ASICs; the report expects its AI-related revenue CAGR to reach about 60% from 2024 to 2029.

  Weaknesses

  Demand is highly dependent on customer capital expenditure, advanced packaging capacity expansion, and supporting data center infrastructure.

  Comparison

  CoWoS capacity is the core benchmark used in the report to measure global AI chip supply and customer allocation.

  Risks

  Power bottlenecks causing end deployment to fall below chip capacity, changes in customer allocation, and execution risks in advanced-node and packaging capacity expansion.

• SK hynix, Micron, Samsung

  Major potential suppliers of HBM3e, HBM4, and HBM4e

  Strengths

  Total AI HBM consumption is expected to increase from up to about 30 billion Gb in 2026 to up to about 50 billion Gb in 2027.

  Weaknesses

  Rubin Ultra's tiered configuration may reduce HBM content per chip for some products, and suppliers must also meet different stack and generation specifications.

  Comparison

  Certifications and allocations across different GPU and ASIC products vary by supplier, and Samsung's participation may increase in some custom ASICs and lower-tier configurations.

  Risks

  Specification downgrades, certification delays, yield, pricing pressure, and new capacity being released faster than demand.

• MediaTek

  Google TPU custom ASIC design partner and potential beneficiary of the 2 nm product supply chain

  Strengths

  The company guides for a 15% to 20% ASIC market share in 2027 and expects its revenue share to increase further in 2028 as 2 nm TPUs ramp.

  Weaknesses

  Revenue growth depends on Google project cadence, advanced-node mass production, and back-end testing capability.

  Comparison

  In parallel with Broadcom's existing TPU projects, MediaTek is expected to expand participation in TPU v8t, v9, and subsequent generations.

  Risks

  Project delays, customer concentration, 2 nm mass production risk, and intensified ASIC competition.

• King Yuan Electronics Co Ltd

  Beneficiary of Google TPU and CPU wafer testing, final test, and system-level testing demand

  Strengths

  Google-related demand is expected to rise from 8% to 10% of revenue in 2026 to 10% to 15% in 2027, and longer testing time and higher complexity are favorable for testing value content.

  Weaknesses

  Related revenue is sensitive to the ramp cadence of single-customer projects, and some revenue has been deferred to the fourth quarter of 2026 and 2027.

  Comparison

  Compared with suppliers that benefit only from chip volumes, KYEC also benefits from higher penetration of burn-in testing and system-level testing.

  Risks

  TPU or CPU shipments below expectations, testing capacity allocation errors, customer concentration, and project deferrals.

• GUC

  Custom ASIC design service provider and potential participant in TPU back-end design

  Strengths

  The company has expressed interest in providing compute chiplet back-end design services for future TPU generations, and the report expects its related CoWoS demand to grow rapidly.

  Weaknesses

  Project wins and revenue recognition depend on customer decisions and product mass production timing.

  Comparison

  Compared with full ASIC partners such as MediaTek and Broadcom, GUC focuses more on design services and customer-customized projects.

  Risks

  Projects failing to materialize, design complexity, advanced packaging capacity, and customer concentration risk.

• Chinese AI GPU vendors

  Building domestic supernode architectures for ultra-large model training and inference

  Strengths

  By connecting multiple racks through NPO, they can scale under domestic supply-chain constraints to support large models with more than 2 trillion parameters.

  Weaknesses

  Constrained by foundry process limitations, the SerDes per-lane rate of domestic GPUs may still be around 100Gb/s, limiting interconnect efficiency.

  Comparison

  Compared with NVIDIA's preferred cross-rack CPO direction, Chinese vendors currently lean more toward near-package optics NPO solutions.

  Risks

  Process nodes, interconnect bandwidth, power consumption, software ecosystem, export controls, and mass production execution risks.

Key data

• Google TPU shipments3.7 million units in 2026; more than 7 million units in 2027The table total shows about 7.35 million units in 2027, mainly contributed by TPU v8i and v8t.
• Google CPU shipments1.5 million units in 2026; 3 million units in 2027Related projects require burn-in testing and system-level testing.
• Google-related business as a share of KYEC revenue8% to 10% in 2026; 10% to 15% in 2027Includes TPU, CPU, final test, and some wafer testing revenue.
• MediaTek's ASIC market share guidance15% to 20% in 2027The company believes that as 2 nm TPU products ramp, its revenue share may continue to rise in 2028.
• Blackwell shipment forecast5.4 million units in 2026The report believes chip supply will be sufficient to meet Grace Blackwell NVL72 demand in the second half of 2026.
• Rubin and Rubin Ultra shipment forecastApproaching 7 million units in 2027Rubin is expected to begin ramping in the third quarter of 2026, with rack shipments starting in the fourth quarter.
• Rubin NVL72 rack shipmentsAbout 90,000 sets in 2027The forecast is based on the chip-and-rack consumption matching model.
• 2027 CoWoS-implied AI chip volumeAbout 19 million unitsAssuming an average of 2 kW per chip, this corresponds to about 38 GW of power demand.
• AI HBM consumptionUp to about 30 billion Gb in 2026; up to about 50 billion Gb in 2027The estimate covers AI GPUs and major cloud vendor ASIC configurations.
• AI wafer consumption valueAt least US$26bn in 2026; at least US$59bn in 2027Estimated based on accelerator shipments, chiplet counts, process nodes, and wafer prices.
• Global CoWoS total demand YoY growth102% in 2026; 93% in 2027Demand growth is jointly driven by customers including NVIDIA, Broadcom, AMD, and GUC.
• TSMC's AI-related revenue growthExpected CAGR of about 60% from 2024 to 2029Covers general-purpose AI chips, custom ASICs, CoWoS and wafer testing, and AI server CPUs.

Impact & implications

The impact on the industry chain is not one-directional. Tiered HBM configurations can alleviate high-end memory supply pressure and reduce system costs, but lower HBM capacity per chip may suppress memory content value, while higher chip shipments benefit wafer, packaging, testing, and other volume-driven suppliers. Kyber delays are unfavorable for new rack adoption in the short term, but may extend the lifecycle of Oberon NVL72 and related PCB, cooling, and system supply chains. Larger-scale supernodes will increase the importance of CPO/NPO, high-speed interconnects, and optical components. Upward revisions to Google TPU and CPU demand directly enhance opportunities for MediaTek, GUC, KYEC, and related advanced packaging and testing segments. In the long term, the greatest constraint may gradually shift from chip capacity to power, data center construction, and system-level cooling capability.

Risks

• Persistent HBM shortages or certification delays could lead to changes in Rubin Ultra's final specifications and ramp cadence.
• Lowering HBM specifications may have a relatively significant impact on decoding performance for long-context large models.
• Kyber server racks are affected by PCB, cooling, and system engineering issues, and delivery timing remains unclear.
• Global power, data center construction, and grid-connection capabilities may be unable to support the forecast AI accelerator installation scale.
• Expansion of CoWoS, advanced-node wafers, or testing capacity may mismatch actual demand.
• Cloud vendor capital expenditure, Google TPU and CPU, or Rubin project shipments may fall below expectations.
• There is uncertainty around CPO/NPO technology roadmaps, yield, cost, and mass production timing.
• U.S. executive orders, export controls, and related transaction restrictions may affect certain companies and securities.
• Morgan Stanley has shareholding, investment banking, or other business relationships with multiple covered companies, which may create potential conflicts of interest.

What to watch

• NVIDIA's final decision on Rubin Ultra HBM specifications before the end of the third quarter of 2026.
• The actual impact of different HBM configurations on decoding, prefill, and long-context large model performance.
• The clear mass production timeline for Kyber racks and progress in resolving PCB and cooling issues.
• The adoption ratio of CPO and NPO as Oberon NVL72 scales toward NVL576.
• Execution of Rubin's volume ramp in the third quarter of 2026 and rack shipments in the fourth quarter.
• The extent to which forecasts of more than 7 million Google TPUs and 3 million CPUs in 2027 are realized.
• MediaTek's revenue share in TPU projects and progress of 2 nm products.
• KYEC's burn-in testing and system-level testing capacity utilization and Google-related revenue contribution.
• TSMC CoWoS customer allocation, capacity expansion cadence, and AI-related revenue growth.
• Global AI data center power capacity, grid-connection progress, and cooling infrastructure construction.